ADS127L01: Sample SPI code

I'm running the code below, but always get back all 0x0 even though I'm writing to several registers.  Do you see anything I'm missing?

#include <msp430.h>

unsigned char MST_Data1,MST_Data2,SLV_Data;
unsigned char temp,A2D_data1,A2D_data2,A2D_data3,A2D_data4,A2D_data5,A2D_data6,A2D_data7,A2D_data8;

int main(void)
{
  volatile unsigned int i;

  WDTCTL = WDTPW+WDTHOLD;                   // Stop watchdog timer

                                            // Set P1.1 for slave reset
  P1DIR |= 0xE0;                            // Set P1.5-7
  P4SEL |= BIT4+BIT5;                       // P3.3,4 option select
  P4SEL |= BIT0;                            // P2.7 option select
 
  UCA1CTL1 |= UCSWRST;                      // **Put state machine in reset**
  UCA1CTL0 |= UCMST+UCSYNC+UCCKPL+UCMSB;    // 3-pin, 8-bit SPI master
                                            // Clock polarity high, MSB
  UCA1CTL1 |= UCSSEL_2;                     // SMCLK
  UCA1BR0 = 0x02;                           // /2
  UCA1BR1 = 0;                              //
  UCA1MCTL = 0;                             // No modulation
  UCA1CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
  UCA1IE |= UCRXIE;                         // Enable USCI_A0 RX interrupt

  P1OUT &= ~0x20;                           // Now with SPI signals initialized,
  for(i=50;i>0;i--);                        // Wait for slave to initialize
  P1OUT |= 0x20;                            // reset A2D

  for(i=50;i>0;i--);                        // Wait for slave to initialize

  MST_Data1 = 0x20;                          // Initialize data values
  MST_Data2 = 0x08;                          // Initialize data values
  SLV_Data = 0x00;                          //

  P1OUT &= ~0x80;                           // A2D CS low

  while (!(UCA1IFG&UCTXIFG));               // USCI_A0 TX buffer ready?
  UCA1TXBUF = 0x07;                     // Reset A2D

  for(i = 20; i>0; i--);                // Add time between transmissions to
                                        // make sure slave can process information
  while (!(UCA1IFG&UCTXIFG));               // USCI_A0 TX buffer ready?
  UCA1TXBUF = 0x42;                     // OFC0
  for(i = 20; i>0; i--);                // Add time between transmissions to
  while (!(UCA1IFG&UCTXIFG));               // USCI_A0 TX buffer ready?
  UCA1TXBUF = 0x01;                     // OFC0
  for(i = 20; i>0; i--);                // Add time between transmissions to
  while (!(UCA1IFG&UCTXIFG));               // USCI_A0 TX buffer ready?
  UCA1TXBUF = 0x55;                     // OFC0
  for(i = 20; i>0; i--);                // Add time between transmissions to
  while (!(UCA1IFG&UCTXIFG));               // USCI_A0 TX buffer ready?
  UCA1TXBUF = 0xAA;                     // OFC0

  for(i = 20; i>0; i--);                // Add time between transmissions to
                                        // make sure slave can process information
  while (!(UCA1IFG&UCTXIFG));               // USCI_A0 TX buffer ready?
  UCA1TXBUF = MST_Data1;                     // Transmit first character

  for(i = 20; i>0; i--);                // Add time between transmissions to
                                        // make sure slave can process information

  while (!(UCA1IFG&UCTXIFG));               // USCI_A0 TX buffer ready?
  UCA1TXBUF = MST_Data2;                     // Transmit first character

  for(i = 20; i>0; i--);                // Add time between transmissions to

  P1OUT |= 0x80;                            // A2D CS high
  for(i = 20; i>0; i--);                // Add time between transmissions to


  __bis_SR_register(LPM0_bits + GIE);       // CPU off, enable interrupts
}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_A1_VECTOR
__interrupt void USCI_A1_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_A1_VECTOR))) USCI_A1_ISR (void)
#else
#error Compiler not supported!
#endif
{
  volatile unsigned int i;

  switch(__even_in_range(UCA1IV,4))
  {
    case 0: break;                          // Vector 0 - no interrupt
    case 2:                                 // Vector 2 - RXIFG
         P1OUT &= ~0x80;                           // A2D CS low

        while (!(UCA1IFG&UCTXIFG));           // USCI_A0 TX buffer ready?
        A2D_data1 = UCA1RXBUF;
        UCA1TXBUF = 0x0;                 // Send next value

        for(i = 20; i>0; i--);                // Add time between transmissions to
                                              // make sure slave can process information
        while (!(UCA1IFG&UCTXIFG));           // USCI_A0 TX buffer ready?
        A2D_data2 = UCA1RXBUF;
        UCA1TXBUF = 0x0;                 // Send next value

        for(i = 20; i>0; i--);                // Add time between transmissions to
                                              // make sure slave can process information
        while (!(UCA1IFG&UCTXIFG));           // USCI_A0 TX buffer ready?
        A2D_data3 = UCA1RXBUF;
        UCA1TXBUF = 0x0;                 // Send next value

        for(i = 20; i>0; i--);                // Add time between transmissions to
                                              // make sure slave can process information
        while (!(UCA1IFG&UCTXIFG));           // USCI_A0 TX buffer ready?
        A2D_data4 = UCA1RXBUF;
        UCA1TXBUF = 0x0;                 // Send next value

        for(i = 20; i>0; i--);                // Add time between transmissions to
                                              // make sure slave can process information
        while (!(UCA1IFG&UCTXIFG));           // USCI_A0 TX buffer ready?
        A2D_data5 = UCA1RXBUF;
        UCA1TXBUF = 0x0;                 // Send next value

        for(i = 20; i>0; i--);                // Add time between transmissions to
                                              // make sure slave can process information
        while (!(UCA1IFG&UCTXIFG));           // USCI_A0 TX buffer ready?
        A2D_data6 = UCA1RXBUF;
        UCA1TXBUF = 0x0;                 // Send next value

        for(i = 20; i>0; i--);                // Add time between transmissions to
                                              // make sure slave can process information
        while (!(UCA1IFG&UCTXIFG));           // USCI_A0 TX buffer ready?
        A2D_data7 = UCA1RXBUF;
        UCA1TXBUF = 0x0;                 // Send next value

        for(i = 20; i>0; i--);                // Add time between transmissions to
                                              // make sure slave can process information
        while (!(UCA1IFG&UCTXIFG));           // USCI_A0 TX buffer ready?
        A2D_data8 = UCA1RXBUF;
        UCA1TXBUF = 0x0;                 // Send next value

        for(i = 20; i>0; i--);                // Add time between transmissions to
                                              // make sure slave can process information
        P1OUT |= 0x80;                            // A2D CS high

        for(i = 20; i>0; i--);                // Add time between transmissions to
                                              // make sure slave can process information
      break;
    case 4: break;                          // Vector 4 - TXIFG
    default: break;
  }
}

Hi Stephen,

It is very difficult for us to read through a portion of someone's code and fully understand the problem. The easiest way for us to verify the interface is by looking at a scope capture of the ADS127L01 SPI signals from a logic analyzer. These would include SCLK, DIN, DOUT, /DRDY, /CS, and CLK.

Before trying to read/write to the ADS127L01, I would suggest verifying that all supplies and clock signals are present as expected. As long as you are sending the master clock (CLK) and START is pulled high, you should notice that the /DRDY pin is toggling at the output data rate. This indicates that the ADC is converting and outputting new data. Have you verified this yet?

Please provide the configuration of all Hardware Mode Pins on your ADS127L01 as well as the supply voltages and clock input frequency. If you'd like, I can review your schematic.

Best Regards,

Thanks Ryan.

Yes, I have verified all the pins on the chip are at expected levels.  Also verified that /DRDY is toggling high once every 4 usec, for about 250nsec whenever the START pin is high.

Schematic attached.  

The problem I'm having is that I'm just doing a simple read of the 8 registers, expecting to read the same data every time.  Instead I usually get all zeros, and sometimes other random data.  I never see the ID register with a 0x3 in the lower nibble as expected.

Steve