Hi:
I'm currently using a FMC144 card (designed by 4DSP) on Xilinx's FPGA vc707, and when I'm configure the DAC chip on this card, which is dac38j84, I have some error message shows up, which is corresponding to jesd interface.
The setting i'm using is here:
uint32_t reg_3B = 0x0000;
uint32_t reg_31 = 0x6408;
uint32_t reg_32 = 0x0270;
uint32_t reg_33 = 0xCD1C;
uint32_t reg_25 = 0x2000;
uint32_t reg_3E = 0x0128;
uint32_t reg_3C = 0x0228;
uint32_t reg4B = 0x1000;
uint32_t reg4C = 0x1F07;
uint32_t reg4D = 0x0300;
uint32_t reg4E = 0x0F4F;
uint32_t reg4F = 0x1cc1;
uint32_t reg_5F = 0x0123;
uint32_t reg_60 = 0x4567;
uint32_t reg_46 = 0x0044;
uint32_t reg_47 = 0x190A;
And my the input reference clock of the DAC is 312.5MHz. So the register value above is setting to get an output data rate as 312.5 MSPS.
After I finished the configuration, I read the values of register 64 to register 6B. The value I got is 0x0103, and since in 4 DSP's reference design, they said if last two bits are 10 and 11, that's fine. So i checked the error code for this value and it says that: 8b/10b disparity error. I don't know what is causing this error and how to fix this.
Hope you can help me with this problem
Thanks
Kevin