Part Number: ADS1672
Hello:
I am currently designing a new product that will be using the ADS1672 ADC. This is a part that I have not used before and there are things about the serial output that I am finding confusing. Please review using Fig. 2 Data Retrieval Timing with External SCLK (SCLK_SEL = 1).
In my design the CSbar input will be tied to ground. The chip will also be set up to use an "External" SCLK and CMOS outputs. In my design I will be using a START pulse (100 nS long). When the DRDY pin goes high (1) and then low (0) the falling edge will cause the external SCLK to start (rising edge first). This the point at which I am confused. In the timing diagram it shows the MSB is available at the rising edge of the SCLK signal and definitely available on the falling edge. It shows the rising edge of the second SCLK pulse lining up with the back end of the MSB availability window and NOT the start of the second MSB availability window. Usually these diagrams show the clock edges coincide with the cross-over points on the DOUT signals. In the diagram there does not seem to be any relationship between the SCLK and the DOUT data. Obviously the SCLK is used to shift the 24 bit result of the AD conversion to the DOUT pin starting with the MSB. Right now my assumption is that when the DRDY pin goes high the result is already in the serial out register but not available on the DOUT pin. Correct? Then on the rising edge of the first SCLK pulse the value of the MSB is passed to the DOUT pin (which I assume is a one bit latch with tristate out) and the other bits are shifted one flip-flop closer to the MSB end of the shift register. Correct? On the rising edge of the next SCLK pulse the MSB value (what used to be the second MSB value) is shifted out to the DOUT pin and the other bits shift forward like the previous cycle. Correct? My assumption is that this process continues until all 24 bits are passed to the DOUT pin. Correct? Now in my circuit I need to input that serial data into a 24 bit serial to parallel register that is being used to interface with the memory chips in the circuit design. If what I assume is correct then it is obvious that all I have to do is have my serial to parallel register clock in the data on the fall edge of SCLK but if the operational timing is as shown in the diagram above I don't think that is possible. It's too bad that the ADC doesn't have a parallel output as it sure would simplify my design. Anyways, can someone tell me if my assumptions indicated above are correct as my design is on hold until I get this taken care of.
On another note regarding the ADC chip. It would have been even better if the device had an internal counter that counted the number of SCLK pulses and locked out the SCLK signal once the last conversion bit was shifted to the DOUT pin until the next DRDY signal occurred.
regards,
Mike Lacroix
