• State Resolved
  • Locked Locked
  • Replies 14 replies
  • Subscribers 47 subscribers
  • Views 1283 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1278 SCLK DOUT timing question

Jason Martin
Prodigy 100 points
Other Parts Discussed in Thread: ADS1278, ADS1178, ADS1274

Hello,

I am using the ADS1278 in a design where it is connected to an FPGA.  The design works fine but I am working to tighten up the FPGA constraints and I don't understand one of the timing specs in the datasheet.  I'm trying to figure out how to constrain the DOUT connection based on the tDOPD spec (SCLK falling edge to new DOUT valid (propagation delay)).  It is spec'd at 31ns which I take to mean it could take up to 31ns from the falling edge of SCLK until DOUT takes on its next value.  If that spec is correct, how can I be confident that my design will work if I use a clock period close to or shorter than 31ns?  The tDIST and tDIHD setup and hold specs seem to mandate a 12ns data valid window centered on the falling edge of SCLK.  With a 27ns clock period, tDOPD would need to be a max of 21ns to meet the 6ns tDIST setup spec.

I think that maybe I am interpreting the values incorrectly or maybe I am missing something altogether.  Can anyone point me in the right direction.

One more observation: The ADS1178 has the same 31ns tDOPD and 6ns tDIST specs.  The minimum clock period for the ADS1178 is 37ns instead of 27ns which works out well because 37-6=31.

Thanks,
Jason

  • 0
    TI__Guru* 97945 points

    Jason,


    I'm not that familiar with the digital section of the ADS1278 (I generally know more about data converters from the analog side of things).

    However, in my reading of the datasheet, the tDOPD is 32ns not 31ns.

    Additionally, the tCLK period is a minimum of 37ns and the tSCLK is a minimum of tCLK which makes that also 37ns. Therefore, the fastest that SCLK and CLK can be run is 27MHz. With that you'd never have a 27ns clock period. Looking at the datasheets, the ADS1278 (page 8) and the ADS1178 (page7) have the same timing requirements.

    If your datasheet reads differently, or if I've completely missed the point (which is possible), let me know.


    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 100 points

    Joseph,

    I should have pointed out that I am using the device in the Frame-Sync mode instead of SPI so I can run at the higher sampling rates.  Page 9 of the ADS1278 datasheet has the specs for the Frame-Sync mode.

    Thanks -- Jason

  • 0 in reply to Jason Martin
    TI__Guru* 97945 points

    Thanks - I'll ask around and see if I can find out.


    Joseph Wu

  • 0 in reply to Jason Martin
    TI__Guru* 97945 points

    Jason,


    I've checked with the development group and this is what I've discovered.

    When the ADS1278 was originally introduced, the part was characterized with CLK at 27Mhz, and the original limitations in the timing diagram were set with this frequency including it's relation to the SCLK frequency.

    After the part was introduced, the part was later characterized to operate at a faster 37MHz, which explains the min CLK period to be 27ns. This was done for operation only in High-Speed mode using Frame Sync format. A limit of 10 channels can be read in the combined TDM mode and high speed mode (see page 33). 

    Regardless, daisy chaining two ADS1278 in high speed is not possible in any event (37ns or 27ns clock), so the timing margin of DOUT propagation delay to the DIN set-up time does not apply. Also note that tDOPD is not related to tCLK. The DOUT is not latched into the SCLK domain and the propagation delay is independent of the CLK timing. The delay is related to other factors such as temperature and digital voltage. If you notice the table for the timing requirements for Frame Sync Format, it lists the values for the entire temperature range and for IOVDD=1.65V to 3.6V.

    Running Frame Sync format at such a high speed requires DVDD to be within 2.0V to 2.2V according to Table 6. By constraining DVDD, this lowers the tDOPD timing to allow for clocking SCLK faster to get valid data. Furthermore, the testing done for higher frequency also looked at Daisy-Chaining at the highest possible rate so that fSCLK=fCLK.

    That's the background. I'll see if I can dig up more details, but that is all I have for the moment.


    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 100 points

    Joseph,

    That is helpful info.

    Even though you can't daisy chain two ADS1278s together (with all channels active), I would think that you could daisy chain two ADS1274s together with all channels active and therefore the DOUT to DIN specs for daisy-chaining should be relevant. 

    In my system, fSCLK=fCLK (they are physically tied together).  I figured that tDOPD was independent of CLK timing but what did you mean by DOUT is not latched into the SCLK domain?  I thought that DOUT would be latched in the SCLK domain and not the CLK domain.

    Ultimately, I need a better idea of what tDOPD is under more constrained operating conditions.  I probably need it to be less than or equal to 21ns to give my application some margin.

    Do you know what was discovered during the higher frequency testing while daisy chaining at the highest possible fSCLK=fCLK rate?

    Thanks again, Jason Martin

  • 0 in reply to Jason Martin
    TI__Guru* 97945 points

    Jason,


    You're right about this being applicable to daisy chaining two ADS1274's. It was something that was discussed when considering this application. However, the development group reasoned that daisy-chaining two ADS1274s was unlikely because there is an ADS1278 available.

    Your second question comes from a mistake of mine. You're right, I'd ment to say that tDOPD is not latched into the CLK domain.

    I'll see if I can get more information about the tDOPD and how fast fSCLK was clocked.


    Joseph Wu 

  • 0 in reply to Joseph Wu
    Prodigy 100 points

    Joseph,

    Like you said, it wouldn't make much sense to chain a pair of ADS1274s.  I'm only discussing it because I am using one ADS1278 in high-speed TDM mode connected to my FPGA which is similar to a daisy-chained setup.  I was reasoning that if I set my FPGA constraints to the same as the DIN timing requirements, I would get a working system.

    I look forward to getting more details.

    Thanks, Jason

  • 0 in reply to Jason Martin
    TI__Guru* 97945 points

    Jason,


    In the interim, can you let me know how you are using the ADS1278? Particularly, I'd like to know if you are using the daisy chain mode, what voltages your supplies are, and any other information about the setup that might be applicable to your question.


    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 100 points

    Joseph,

    We aren't using the daisy chain mode.  The ADS1278 is connected directly to our FPGA.  We are using the Frame-sync High-speed TDM Fixed mode.

    AVDD is 5v.  IOVDD is 3.3v.  DVDD is 1.8v (the older revision of the datasheet didn't say anything about the effects of using a slightly higher DVDD voltage).

    CLK and SCLK are 32MHz.

    Jason

  • 0 in reply to Jason Martin
    TI__Guru* 97945 points

    Jason,

     

    Just to let you know, we're still evaluating this. I understand your concerns about tDOPD, but it may take some time to review our current data and figure out if there's any other data we need to pull in that spec for the faster case.

    Out of curiosity, what is the tolerance on your DVDD spec?

     

    Joseph Wu

  • 0 in reply to Joseph Wu
    TI__Guru* 97945 points

    Jason,


    Again, we're still looking, but we've run a few tests and this is where we think it will come out over temperature:

    DVDD = 1.7V to 2.2V

    IOVDD = 3.3V +/-5%

    TDM mode tDOPD for DOUT1 ~20-22ns

    for other DOUTs, add about 2-3ns

    At room temperature, the DOUT1 propagation delay ended up being about 14-16ns.

    We'll try to have something more specific next week.


    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 100 points

    Joseph,

    That is very helpful.  With numbers like that, I can have some confidence in the margins of our design.

    In TDM mode, would the other DOUTs ever be used?

    Thanks, Jason

  • 0 in reply to Jason Martin
    TI__Mastermind 43915 points

    Hi Jason, 

    When using TDM mode all of the channels outputs are routed out of DOUT1. The other DOUT pins (DOUT2-DOUT8) are not used for any reason and can be left floating. 

    Regards,

    Tony Calabria 

  • 0 in reply to Joseph Wu
    TI__Guru* 97945 points

    Jason,


    The development group took a look over temperature and these will likely be the specs to be added to the datasheet:

    FRAME-SYNC Mode

    tDOPD and tMSBPD

    DOUT1, TDM Mode, DVDD: 2V to 2.2V, IOVDD: 3.15V to 3.45V:                           20ns (max)

    DOUT1, TDM Mode, DVDD: 1.7V to 1.9V, IOVDD: 3.15V to 3.45V:                        24ns (max)

    SPI Mode

    tDOPD

    DOUT1, TDM Mode, DVDD: 1.7V to 1.9V, IOVDD: 3.15V to 3.45V:                        26ns (max)

     

    Joseph Wu