Hello,
I am using the ADS1278 in a design where it is connected to an FPGA. The design works fine but I am working to tighten up the FPGA constraints and I don't understand one of the timing specs in the datasheet. I'm trying to figure out how to constrain the DOUT connection based on the tDOPD spec (SCLK falling edge to new DOUT valid (propagation delay)). It is spec'd at 31ns which I take to mean it could take up to 31ns from the falling edge of SCLK until DOUT takes on its next value. If that spec is correct, how can I be confident that my design will work if I use a clock period close to or shorter than 31ns? The tDIST and tDIHD setup and hold specs seem to mandate a 12ns data valid window centered on the falling edge of SCLK. With a 27ns clock period, tDOPD would need to be a max of 21ns to meet the 6ns tDIST setup spec.
I think that maybe I am interpreting the values incorrectly or maybe I am missing something altogether. Can anyone point me in the right direction.
One more observation: The ADS1178 has the same 31ns tDOPD and 6ns tDIST specs. The minimum clock period for the ADS1178 is 37ns instead of 27ns which works out well because 37-6=31.
Thanks,
Jason