DAC5662: DAC5662 Data Interface,timing and modes.

Nikita Alisov

Part Number: DAC5662
Other Parts Discussed in Thread: DAC5652, DAC5672,

I'm working on a device that contains several DACs. I want conect several DACs to one bus, and use apart WRT(IQ) and CLK(QI) input. I have questions about managing the DAC.

1) In the datasheet it is written that after setting the data on the bus D[11:0], I must set the "WRT" control signal and after the rising edge of the signal, I should wait for time tlat = 4 clk for "Clock latency (WRTA/B to outputs)". What is the time tlat? What "outputs" by meant? And what is meant by these 4 clk? Time equivalent to four frequency periods? What frequency WRT1 or CLK?
Or to set the values in the latch, I have to generate 4 pulses WRT or CLK?

I found PDF document "DAC5652, DAC5662 and DAC5672 Interleaved Data Mode" with filename "X2_Interleaved_Mode.pdf". In it document nothing written about 4 clk.

2) In the datasheet it is written that after setting the data on the bus D[11:0], in Dual-Bus mode, I must set the "WRT" control signal to tlph=2ns. What about this time in Single-Bus mode?

3) In the Single-Bus mode, the CLKIQ frequency is divided by 2 and then go to the DAC latch. What is it done for? What could connect two inputs CLK & WRT?

P.S. Sorry for my English =(

Thanks a lot, with best wishes, Nikita Alisov.

over 8 years ago

0 Neeraj Gill over 8 years ago

TI__Mastermind 20541 points

Hi Nikita,

1. Data is latched in the DAC with the rising edge of WRTA/B and it will take tlat+tpd = (4 clk cycle or periods + 1.5ns) for input data to show up on the output pin Iout(output). Yes 4 clock cycles are equal to 4 clock periods. The WRT1 and CLK1 should be equal to each other in frequency and it will depend on your dac output rate. You don't have to generate 4 pulses. Your WRT AND CLK should be running continously and once the data is latched on rising edge of WRT after 4 clock period + 1.5ns you should see continous signal at the output of the dac.

2. In single bus mode you will have to maintain the timing shown in figure 19 in the datasheet.

3. In sigle bus mode I and Q data is applied on DA0.....DA11 as a result the I-channel input data rate is twice the update rate of the DAC Core and CLKIQ(CLKA) and WRTIQ(WRTA) are toggling at twice that speed. In single clock mode your clock will connected to CLKIQ pin. WRT will connected two WRTIQ pin, ResetIQ is connected to CLKB pin and SelectIQ is connected to WRTB pin.

Regards,
Neeraj Gill

0 Nikita Alisov over 8 years ago in reply to Neeraj Gill

Prodigy 20 points

Ok. If I want for example 8 independent analog outputs and i want change level on all 8 Outputs in one time i must do one clock impulse. I can't running CLK all time!
If i will do schematics like in figure 1, one FPGA or uC, 4 DAC5662, one BUS for 12 bit data line, one CLK, one RESETIQ and independeds from all DAC inputs: WRT and SELECTIQ. Is this possible in principle?

Figure 1:

To the scheme I mentioned above, I drew the time diagrams, based on how I understood the algorithm of the DAC5662.

If it's possible, confirm my case or show my mistakes in this.

I'm looking forward to it, thank you very much.

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DAC5662: DAC5662 Data Interface,timing and modes.