We are designing the ADS1271 A/D converter into a new product, and have a question regarding the timing of this component. When operating in the Frame-Sync mode, Figure 51 in the data sheet indicates that the width of FSYNC is very small relative to the CLK line, even though the diagram on Sh.7 "Timing Characteristics: Frame-Sync Format" and the associated text specify that the width of FSYNC must be a multiple of the CLK width. We must know the exact relationship of FSYNC to the CLK and SYNC/PDWN pins before proceeding further. Thanks in advance for your help...