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ADS1271 timing

bigdog
Intellectual 305 points
Other Parts Discussed in Thread: ADS1271

We are designing the ADS1271 A/D converter into a new product, and have a question regarding the timing of this component. When operating in the Frame-Sync mode, Figure 51 in the data sheet indicates that the width of FSYNC is very small relative to the CLK line, even though the diagram on Sh.7 "Timing Characteristics: Frame-Sync Format" and the associated text specify that the width of FSYNC must be a multiple of the CLK width. We must know the exact relationship of FSYNC to the CLK and SYNC/PDWN pins before proceeding further. Thanks in advance for your help...

  • TI__Mastermind 43915 points

    Hi Bigdog,

    The FSYNC signal is used to time out the communication between the ADC and controller. The signal should pulse after SCLKs have been pulsed out to read back the data. Generally, we recommend that the SCLK signal is a multiple of the CLK signal in order to minimize the noise as much as possible. The FSYNC should pulse after all the data has been clocked out. That is why we typically spec that the period of a FSYNC is 256 or 512 CLK cycles. The time that the FSYNC signal needs to be high or low is one SCLK period as stated in the timing specs on page 7 of th data sheet. The characteristics for the /SYNC/PWDN pin is on page 20 of the data sheet.

    I understand your worry, in Figure 51, it does look like the the SYNC pin is very small relative to the CLK line. However, the page 7 timing specs are the numbers to follow.

    If you could, draw out a timing diagram of how you plan to have your timing set up. I will take a look at it to let you know if I have any concerns.

    Regards,

    Tony Calabria