• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 47 subscribers
  • Views 1067 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1675: And ADS127I01:

Leo Bredehoft58
Expert 1260 points
Part Number: ADS1675
Other Parts Discussed in Thread: ADS127L01

I have an electrically-isolated conversion application which ideally would avoid ADC clock distribution across an isolation barrier. I hope to run the circuit at 1M samples/second with the ADS1675 or 512K samples/second with the ADS127I01.  The ADS1675 data sheet specifies tSTART_CLKR, and the ADS127I01 data sheet specifies tsu(ST), as setup times of START to CLK.  Is there a combinatorial path inside of these ADC's from START rising edge directly to the sample-and-hold capacitor switch, making START the critical control signal, or is START first synchronized to CLK to generate the switch control signal, making CLK the critical control signal?  The answer to this question determines whether my design must make START synchronous to CLK and synchronize CLK to the remainder of the system, over the isolation barrier, or simply run an otherwise-asynchronous START across the isolation barrier with no other sample control support.

Thanks for your help!

  • 0
    TI__Guru**** 181511 points
    Hi Leo,

    There is nothing inside the ADS1675 that links START directly to (or through combination logic) the sample and hold switch. The S/H is controlled by the clock signal, START is there as a means to synchronize multiple devices and control when the conversion sample period starts. Assuming you are pulsing START, and if you need precise control and repeatable conversion periods, you would ideally synchronize the START and CLK signals. If you can tolerate +/- 1/2 CLK uncertainty in the settling time, you can use START in an asynchronous manner. If you bring START high and leave it high to get continuous conversions, there would only be uncertainty in the first settling period without synchronizing to the CLK.
  • 0 in reply to Tom Hendrick
    Expert 1260 points
    Thanks. That's the answer I was looking for.
  • 0 in reply to Leo Bredehoft58
    TI__Guru 66746 points
    Hi Leo,

    Regarding the ADS127L01, CLK is the important signal that controls the sample-and-hold timing, not START. However, I am not sure why the low-to-high transition on START must occur at least 10ns before the CLK rising edge - I'd have to ask a designer. However, when pulsing the START pin, I suppose the easiest thing to do is to synchronize it with the inverse of CLK and ensure the pulse width is at least 4 CLK periods.

    If you do not need to synchronize START to an external event or to other ADCs, then I would leave START pulled up at power up for continuous conversions.

    Best Regards,