ADC12D1000: Doubling Data Output Rate

Amanda Ross95

Part Number: ADC12D1000
Other Parts Discussed in Thread: ADC12D1600

Hello,

I have a customer who is currently working with the ADC12D1000 using a 667MHz sample clock while also using demux and non-des modes. He is thinking of switching to the ADC12D1600 with a sample clock of 1.33GHz as he wants to double the data output rate.

If he does decide to take this avenue and do the switch to the ADS12D1600, would everything else also double (i.e. DCLK_I and DCLK_Q for example)?
On the other hand, if he were to stick with the ADC12D1000, it seems as though he would only be able to increase the current data rate by 50% max by changing his existing 667MHz sample clock to a 1GHz sample clock. Is this the case or do you know of a way to stick with the ADC12D1000 and still be able to double the data rate?

Appreciate any feedback you can provide on this!

-Amanda

over 9 years ago

0 Jim Brinkhurst1 over 9 years ago

TI__Mastermind 44680 points

Hi Amanda

You are correct, if the customer wants to double the sample rate and corresponding output data rate, then they need to migrate from the ADC12D1000 to the ADC12D1600. The ADC12D1000 max clock rate is 1000 MHz. The ADC12D1600 will support their needed clock rate of 1333 MHz.

The output DCLK and Data rates will all double, so the data capture solution will now need to handle an output data rate of 667 Mwords per second on each of the output data buses (demux mode)

Best regards,

Jim B

0 Amanda Ross95 over 9 years ago in reply to Jim Brinkhurst1

TI__Intellectual 2740 points

Jim, Thanks so much for the prompt response.

Happy Friday!

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ADC12D1000: Doubling Data Output Rate