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ADS54J42: Data sheet mismatch?

Anders Frykberg
Prodigy 95 points
Part Number: ADS54J42


Hi all,

I'm looking at the ADS54J42 ADC for a customer project. I'm used to the JESD, but there are a few question marks when I read the data sheet.

1) PRBS support. In chapter 8.4.2.2 it is stated that PRBS15 is supported, selected in JESD digital register page. But in the test select register (0x2) there is no PRBS alternative. Is it the RPAT that is used as PRBS?

2) I want to run the device in LMF=421. In table 13 it says JESD_MODE=0x4 and JESD_FILTER=0x0 to select LMF=421.
But in the example Table 16, JESD_MODE=0x2 is used for LMF=421.
Which one is valid?

Best regards,
Anders Frykberg

  • 0
    TI__Guru* 91947 points

    Anders,

    The device does not support PRBS and this will be removed from section 8.4.2.2. We are currently revising the data sheet. See the attached copy.  For the answer to question #2, the JESD_MODE needs to be set to 0x04 for LMF = 421.

    Regards,

    Jim

    SBAS756B_Draft3_01192017.pdf

  • 0 in reply to jim s
    Prodigy 95 points

    Thanx, Jim!

    I note that the table 17 in the draft still says that value 0x2 will give me LMF=421, so there is still a mismatch. But we use value 0x4.

    On other thing we have problems with, is reading back register.

    write 0x005340  # Set "Ignore sysref"
    write 0x805300  # read back of Ignore sysref register.

    This read back 0x40, as expected.

    write 0x6001C4  # Set JESD i "4 lane mode (LMF=421), no decimation", "Syncreg_en, send K28.5".
    write 0xe00100  # read back of JESD \"4 lane mode (LMF=421), no decimation\",\"Syncreg_en, send K28.5\""

    This read back 0x00, as do other registers in the JESD digital page. Why? They are noted to be R/W.

    Regards,

    Anders
        
       

  • 0 in reply to Anders Frykberg
    TI__Guru* 91947 points

    Anders,

    Table 17 is for LMF = 4222 not 421. If you do not have the device clock running and a SYSREF issued, the SPI will not be able to read the JESD digital portion of the device.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 95 points
    Thanks Jim,

    Copy from the draft: Table 17. Two Lanes per Channel Mode (LMFS = 4211)

    Anyhow, we use value 0x4 for the LMF selection.

    As for clocking, the device clock is running. Do we need a sysref to program the device? How can you program it to be a subclass0 device? Or is it just the read back that doesn't work?

    Regards,
    Anders
  • 0 in reply to Anders Frykberg
    TI__Guru* 91947 points

    Anders,

    In section 8.3.4, it describes how to generate a SYSREF pulse using register writes. Are you using a the TI EVM or a custom board?

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 95 points
    God morning Jim,

    It's a custom board.

    Regards,
    Anders
  • 0 in reply to Anders Frykberg
    TI__Guru* 91947 points

    Anders,

    Did you provide a software SYSREF to see if this corrects your read issue?

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 95 points
    Hi Jim,

    Now we tried the manual sysref, and it seems to work! Thanx!

    0x6001C4 # Set LMF = 421, syncreg_en, testmode
    0xE001 reads back C4!

    Do you have any other hidden registers we can use? We'd like so see if the PLL is locked, for instance...

    Regards,
    Anders
  • 0 in reply to Anders Frykberg
    TI__Guru* 91947 points

    Anders,

    This is good news. What PLL are you referring to in your last post? This part does not have a PLL.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 95 points
    Hm,

    No PLL? The block diagram in chapter 8.2 clearly shows a PLL. And register settings in the analog master page have a 20x/40x selection for the PLL. I don't understand.

    Regards,
    Anders
  • 0 in reply to Anders Frykberg
    TI__Guru* 91947 points

    Anders,

    You are correct. There is a serdes PLL that I forgot about. But there is no register that can monitor if this is locked or not. Normally if this is not locked, the JESD link would not have been established. If it was to go out of lock during normal operation. the receiver would start getting 8b/10b errors and would assert SYNC low.

    Regards,

    Jim

  • 0 in reply to Anders Frykberg
    TI__Guru* 91947 points

    Anders,

    Sorry about the last response. I thought you were asking about a sampling clock PLL like we have in our newer DAC's. I replied today to a Bjorn Langels about a register reading issue. It sounded like the same problem you were having. Do you both work together? If so, did the answer help? We are currently working on updating the data sheet and hope to have this released in the near future.  Let me know if you still need any help. 

    Regards,

    Jim