adc32rf45: Questions about data alignment between the two ADC's

Hi,

I have not noticed any skew between the two channels.  I can ask the design team if they are aware of any reason such a thing could occur, but I have not seen such a thing.  Questions I might ask are:  What LMFS mode of operation are you using?  Where are you observing the channel skew?   Are you using a continuously running SYSREF after device configuration or are you turning off SYSREF after config?   Oh, and are you using the device on our EVM into the TSW14J56 or is this on your own hardware.   The reason I ask about SYSREF is that the SYSREF resets the clock dividers on the front of the ADC and if not reset properly then the phase of the internal sampling clocks could be off.  But with just a 2way interleaved RF42 and a clock divided by two, there are not many ways to get the clock phases out of alignment, and even then that would only affect the lane assignment with the channels, not skew between channels.   But if the SYSREF is continuously running then I would next ask if the SYSREF is meeting setup/hold about the sample clock.    Getting a SYSREF edge detected on the wrong multiframe boundary during link operation would cause link disruption I believe, if the SYSREF timing were off relative to clock and if it were continuously running.    We turn off SYSREF on the EVM once a link is configured.  But even then I've not seen that cause skew between channels.

Regards,

Richard P.

LMFS = 4211  K = 32, 14 bit bit mode DDC in bypass

Channel skew is between the two ADC's.  Common signals fed into both channels. 

SYSREF is not continuous.   SYSREF is pulsed four times before.  After the first two times the SYSREF to the CLKDIV is masked.  After the third SYSREF the MASK NCO SYSREF is set.

We have a ADC32RF42 installed on our hardware. 

  Thanks,

Bill

Hi,

My suspicion would be that the two ADCs are not seeing the SYSREF edges at the same time, as in possibly not meeting setup and hiold for SYSREF around the sample clock at one of the devices.  The reason i say that is the the rising edge of SYSREF for a device sets the internal multi-frame clock for that device, and when the SYNC signal is taken away from the ADC then the Initial Lane Alignment ILA sequence begins on the next multiframe boundary.   With the mode being bypass and K = 32, then the multiframe boundary would be 32 samples in length (64 octets) so if the two ADCs received the same SYNC signal but right on the edge of a multiframe bounary, then for one ADC the 'next' multiframe boundary might start right away while the other ADC just missed catching the change in SYNC and the 'next' multiframe boundary would be 64 octets further away.   But that is not the skew being seen.  That makes me think the multiframe boundary inside the ADC is slightly different for each due to when each ADC sees the SYSREF.  but if the sample clock is arriving at the two ADCs with matched lengths and matched ariival time of the clock to the ADCs, and the SYSREF for each ADC also meets the setup and hold time for each device, then the local multiframe clocks should be alighned between the two ADCs.    If the SYNC signal goes away at the same time for each and is safely away from the internal multiframe boundaries, then the ILA should begin at the same time for each.    I've not seen otherwise, but on my EVM i just have the one ADC.  I will ask the design team to review my description here of what i expect to see happen, and see if they see anything i have missed.

Regards,

Richard P.