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ADS1298R: ADS1298 DRDY signal problem，I am very anxious

pingyang_wu
Prodigy 50 points
Part Number: ADS1298R
Other Parts Discussed in Thread: ADS1298

I now use the FPGA control ADS1298 development board, first configure the power to initialize, and then configure the register, and finally convert the data and receive.
The problem is 1. DRDY‘s cycle is unstable, jitter is very powerful, resulting in the output data is wrong, how to stabilize the DRDY’s cycle?
                         2. The data sheet says that the DRDY signal is pulled high on the first falling edge of SCLK, but when should I give the SCLK signal?

  • 0
    TI__Mastermind 38745 points

    Hello Pingyang,

    1. Can you capture this behavior on an oscilloscope or logic analyzer for me to look at?
    2. You can being toggling SCLK after DRDY goes from high to low and after you have asserted CS. The device indicates new data by taking DRDY from nigh to low, so by waiting until after DRDY goes low, you are collecting the newest conversion data.

    Brian