In the May 2016 Addendum for the AD1283 the SPI clock is increased from 2MHz to 4MHz. Does this apply to the DAC1282 also? Are the gap between byte requirements for register access the same for the DAC1282?
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In the May 2016 Addendum for the AD1283 the SPI clock is increased from 2MHz to 4MHz. Does this apply to the DAC1282 also? Are the gap between byte requirements for register access the same for the DAC1282?