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DAC1282: DAC1282 and ADC1283 compatibility

Part Number: DAC1282


In the May 2016 Addendum for the AD1283 the SPI clock is increased from 2MHz to 4MHz.  Does this apply to the DAC1282 also?  Are the gap between byte requirements for register access the same for the DAC1282?

  • Hi George,

    Welcome to the TI E2E forums!

    The DAC1282's SPI interface is a bit different from the ADS128x devices... It can actually have an SCLK frequency of up to 8.333 MHz and does not require a delay between command bytes.

    If you're sharing an SPI peripheral between the two devices, you could implement the SPI timing for ADC (with the slower SLKC frequency and delay between the command bytes) and it should also work for the DAC.

    Best Regards,
    Chris