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DAC38RF80: Deterministic latency when using DAC and ADC with different clock rates (JESD204B)

guy vaisman
Prodigy 230 points

Part Number: DAC38RF80
Other Parts Discussed in Thread: ADC32RF45,

Hi,

I want to sync a DAC (DAC38RF80) , ADC( ADC32RF45) and a FPGA simultaneously and achieve deterministic latency.

Since they don't have the same sampling rates, i can't  find a proper JESD204B configuration parameters (L-M-F-S-HD, K ) that will give me the
same frame clock, local multi frame clock and serdes rate. I did manage to find a combination that will give me the same local multi frame clock and sysref frequency.

Is it still possible to setup a proper link with only the local multi frame clock identical in both devices ?
Also, what are the FPGA clock requirement in such a case?

Thanks in advance,
Guy.

  • 0
    TI__Guru* 91947 points

    Multi-Device Synchronization of JESD204B Data Converters_Apr2016.pptxGuy,

    As long as all three parts are setup for subclass 1 mode, and the SYSREF is source synchronized to the device clock, and all three device clocks are synchronized, you should be able to achieve deterministic latency. See the attached document for more info.

    Regards,

    Jim

      

  • 0 in reply to jim s
    Prodigy 230 points
    Hi Jim,

    In case of using multiple ADCs, is it possible to ensure that all of the ADCs raw sample data will be completely aligned using the JESD204B?
    Is the first frame of valid data marked somehow by control characters?
    For example, the AD32RF45 can have up to 150ps aperture delay difference between different devices, meaning that even in the case of deterministic latency of the JESD204B i will still have a skew of 150ps.

    Same question in case of multiple DACs, how can i make sure that at the analog output, the samples will be completely aligned between the multiple DACs ?

    Thanks,
    Guy.
  • 0 in reply to guy vaisman
    TI__Guru* 91947 points

    Guy,

    Yes, the data will be aligned and the delay will be deterministic for both ADC and DAC's if using subclass 1 or 2. Regarding aperture delay, you are correct. There is no way to guarantee the ADC parts will be sampling the same analog input at the same exact time. But the time the data gets out of all of the devices will be referenced to the same clock cycle in time. This is per the standard as long as you have the RBD set properly and not overflowing the elastic buffers.

    Regards,

    Jim