TVP5158 is not recognized

What registers are you setting?

Are you saying the clock and data outputs do not wiggle?

BR,

Steve

Hello!At the bottom are the register Settings for TVP5158, working patterns

It is the analog CVBS input channel 1, the PAL signal, the output select DVO_1,

The format is 8BIT DI format, but the latter is not recognized by the conversion chip.

The standard DI signal is received and the chip input port is normal。

Register setting：

Signal link：

CVBS IN ----- TVP5158 -----FPGA -----GS2972

1.The current state：

Set TVP5158 to a single mode and the output signal cannot be detected by GS2972.

TVP5158 output clock: 27M;

TVP5158's DVD_A output data entered the FPGA extraction HS.

But when you get rid of the input CVBS, the HS, VS, and OE are normal;

Other tests: the FPGA generates the color bar test chart with the 27M clock output of TVP5158, which is detected by the GS2972.

The output is displayed normally.

2.

TVP5158 set content:

Output TVP5158's own blue field test signal at DVD_A.

Format: 8BITS D1 format.PAL system.

The TVP5158 register is as follows:
00H: 7e b0 03 00 02 00 00 00 51 58 71 02 82 00 ff 03
10H: 80 80 00 80 00 00 70 0a 40 00 00 00 0c 00 00 00
20H: 6a 08 80 80 00 f5 00 00 00 06 1e 04 00 f2 08 04
30H: ff ff 00 00 6a 08 05 07 84 00 d0 02 19 00 20 01
40H: 07 00 47 00 04 00 07 00 84 00 d0 02 6f 02 18 00
50H: 84 00 d0 02 97 00 bc 02 26 00 06 01 1e 09 34 03
60H: 00 09 40 1e 18 00 0b 00 00 1f 1f 02 10 04 64 20
70H: 7d 00 8a 64 04 02 0f 0f 03 05 20 1e 02 08 03 03
80H: 0a 01 5a 06 00 03 22 00 00 12 1d 64 00 00 0a 04
90H: 10 80 80 00 4c 1a 60 50 00 00 00 0a 05 05 03 bc
A0H: bc 00 0d 02 90 01 78 00 00 08 03 d8 05 00 01 00
B0H: 00 ff ff e4 e4 00 71 12 40 00 00 01 d7 0f 00 00
C0H: 00 88 88 c9 01 00 00 00 00 a5 ff 7e 01 00 00 00
D0H: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
E0H: 00 00 00 00 25 25 25 25 54 00 00 00 00 00 00 25
F0H: 08 00 00 00 00 00 00 00 00 25 25 25 25 25 2f 01

3. 

Enter the CVBS (PAL color bar) at VIN_1

The register is the same as the previous one, but A9:40.

With a video signal connected to the input what does the Status 0 register indicate?

Note, with no video connected there will still be a digital output stream, but it will contain black video (depending on how the blue screen registers are configured).

Try changing the 'blue' screen color to something other than black so that we can determine if a valid video input is being detected. Something like 0xaa, 0x55, 0x55 would be good since that is easier to see on a scope/logic analyzer. (On a scope this will present alternating high/low transitions most of the time on most of the data bits.

Also note that what the video is connected/disconnected there will be discontinuities in the digital video stream. The receiving device MUST be able to dynamically re-synchronize to the SAV/EAV codes.

Is the H/V/F output of the FPGA different when CVBS is connected versus not connected? If so, then the FPGA is likely not correctly decoding the SAV/EAV codes.

So, just to clarify... Are you stating that with the blue screen enabled but no CVBS then the GS2972 can correctly display the blue screen, but when you connect CVBS the GS2972 stops displaying a good image?

How much jitter can the GS2972 accept? How are you determining "not recognized by the conversion chip" ? The clockoutput from the TVP WILL have significant jitter since it will be synchronized to the incoming CVBS signal. Using this clock directly to generate a high speed SDI clock may simply not work due to jitter.

First thing to check is the status register to make sure the TVP is detecting a valid video signal, and what that video signal is.
Second, set the 'blue' screen color to something that can be monitored on a scope, and to mode 01.
Third, make sure that the GS2972 and your FPGA correctly re-synchronize to the SAV/EAV codes.
Fourth, check the serializer clock jitter requirements.

BR,
Steve