DAC38RF80: Questions regarding spec

guy vaisman

Prodigy 230 points

Part Number: DAC38RF80

A few questions regarding the dac38RFXX –

Vout1&Vout2 relative amplitude and phase imbalance.

Should I expect any amplitude and phase difference between the two output channels (in all of the temperature range)?

The Digital Latency : JESD Buffer to DAC output, how does it vary across temperature? only typical values are specified. Could you provide more info on this?
The PLL has a very wide Loop filter bandwidth (500KHz), this means the phase noise performance inside the BW should be

designed more carefully. Could you provide data regarding the PLL FOM and 1/F noise? I'm trying to understand what are the phase noise

requirements of the reference clock in order to achieve optimal results.

Thanks in advance,

Guy.

over 7 years ago

0 jim s over 7 years ago

TI__Guru* 91947 points

Guy,

Phase noise data attached. We are looking into your other questions.

Regards,

Jim

DAC38RF8x_PhaseNoise_Measurements.pdf

0 guy vaisman over 7 years ago in reply to jim s

Prodigy 230 points

Hi Jim,

Thanks for the measurements results, very informative.
However, it seems they used an external clock at 6GHz - I'm interested in using the interanal PLL inside the DAC
so i could feed a slower device clock. Do you have any test results for that setup?

Thanks in advance,
Guy.

0 guy vaisman over 7 years ago in reply to guy vaisman

Prodigy 230 points

Hi Jim,

Are there any updates?

Thanks,
Guy.

0 jim s over 7 years ago in reply to guy vaisman

TI__Guru* 91947 points

Guy,

Due to limited resources, we have not had a chance to look at this. What is the application for? The EVM for this device is available if you care to order one.

Regards,

Jim

0 jim s over 7 years ago in reply to jim s

TI__Guru* 91947 points

Guy,

I was able to get some data regarding the PLL from the design team. See attached file.

Regards,

Jim

DAC38RF80_data.xlsx

0 guy vaisman over 7 years ago in reply to jim s

Prodigy 230 points

Hi Jim,

Thank you for sharing the measurement results.

Another question regarding the SerDes PLL -
In the datasheet it is stated the VCO frequency range is 1.5625-3.125GHz.
Also, The SerDes line rate can be as much as twice the SerDes PLL output frequency.

Given this, how can one achieve the maximum 12.5Gbps line rate ?
I've attached the relevant part from the datasheet.

Thanks,
Guy.

0 jim s over 7 years ago in reply to guy vaisman

TI__Guru* 91947 points

Guy,

Why are you asking about max line rate? Are you not really interested in max sampling rate?

Regards,

Jim

0 guy vaisman over 7 years ago in reply to jim s

Prodigy 230 points

Hi Jim,

I'm referring the JESD204B SerDes rate.

I would like to use a SerDes rate as high as possible, in order to reduce the number lanes.

The JESD204B configuration i want to use is L=4,M=8,F=4 so my SerDes rate will be ~9GSPS.

Thanks,

Guy.

0 jim s over 7 years ago in reply to guy vaisman

TI__Guru* 91947 points

Guy,

If you are using an LMF = 484, and sample the DAC at 7.5Gsps, when using 2 IQ pairs, the serdes rate will be 12.5Gbps (max). If you want a serdes rate of 9Gsps, you would need to sample the DAC at 5.4Gsps.

You can use the DAC GUI in simulation mode to help determine what your serdes rate will be based on the DAC settings you plan on using.

Regards,

Jim

0 guy vaisman over 7 years ago in reply to jim s

Prodigy 230 points

Hi Jim,

Another question,
In the datasheet, SYSREF TO JESD LMFC RESET is defined in units of JESD clock cycles.
What rate is a JESD clock cycle?

Thanks,
Guy.

0 jim s over 7 years ago in reply to guy vaisman

TI__Guru* 91947 points

Guy,

The rate is determined by the JESD mode being used. See table 36 of the data sheet or the clocking tab under the DAC38RF8x tab of the DAC38RF8x GUI.

Regards,

Jim

Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

Data converters

Data converters forum

DAC38RF80: Questions regarding spec