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ADS4129: ADC is reading bogus periodic sample

Saril Kaiprath
Prodigy 130 points

Part Number: ADS4129

Hi,

We are using ADS4129 in one of our design. We have an FPGA which reads the DDR LVDS serial DATA from ADS4129. We are trying to fix the bogus sample periodically sampled. The screen shot shows the plot on excel sheet with an input signal of 1MHz and 250mV pp at the input of ADC. The sampling clock is 250MHz.

It would really help us if you have suggestion for debugging this issue. I have also attached the read data in csv format. I would like to know if this could be due to a HW design or PCB Layout issue.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/73/ADS4129_5F00_ADC_5F00_Capture.7z

Thanks,

Saril Kaiprath

  • 0
    TI__Guru* 91947 points

    Saril,

    Make sure you set High performance mode 1 to a "1" and High performance mode 2 to "0". Have you tried adjusting the following registers to see if this helps:

    1. LVDS swing

    2. LVDS CLKOUT strength

    3. LVDS Data strength

    4. CLKOUT rise/fall time delay

    Do you see this issue when sending test patterns out of the ADC?

    Send your schematic and layout and we can take a look at it.

    Regards,

    Jim

     

  • 0 in reply to jim s
    Prodigy 130 points

    Jim,

    Thanks. I tried most of these settings. I will test with the high performance mode 1 and 2 as you mentioned.  Couple of more observations below.

    1. With a higher DC offset on the N input compared to P tends to fix this issue. But seems again this is only for a narrow margin of input offset. Say DC offset at P is around 900mV and N input is around 1.1V. I was testing different input offset and this finding was accidental. Attached another capture here.

    2. Test patterns with all one and all 0s are clean. However the noise sample is seen with ramp input.

    Please check the captures and let me know your comments.

    Thanks,

    Saril

    ADS4129_capture_issues.zip

  • 0 in reply to Saril Kaiprath
    TI__Guru* 91947 points

    Saril,

    I think this may be a timing problem with your FPGA. Try capturing data at a lower sample rate to see if this corrects this.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 130 points

    Jim,

    Thanks. Let me try to change the sampling clock to 125MHz and test. Will let you know the results.

    Thanks,

    Saril

  • 0 in reply to jim s
    Prodigy 130 points
    Hi Jim,

    This is to let you know and close this request that, the issue was with the FPGA DDR sampling. FPGA guys were able to tune the reference clock and align with the data window to fix this timing issue. Thank you very much for your timely support.

    Thanks,
    Saril
  • 0 in reply to Saril Kaiprath
    TI__Guru* 91947 points

    Saril,

    Thanks for the feedback.

    Regards,

    Jim