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CCS/ADS1291: ADS1291 Noise Problem

Ferhat Bayir
Intellectual 290 points
Part Number: ADS1291

Tool/software: Code Composer Studio

Hello I have my own design with ADS1291

I have noise problem and cant get a clear signal.

Its being very bad with 500 sps, below pictures with 250sps. Gain set to 1. 

When i touch my hand to patient simulator, its being clear for two pulses than same.

My registers;

0x00, //ID
0x01, //Sample Rate
0xA0,
0x10,
0x00, //CH1
0x81, //CH2
0x00, //RLD SENS
0x00,
0x00, //2.048MHz Select
0x02, //Respiration Off
0x07,

I tried connecting un used RLDINV, RLDREF to VDD.

Regards

Ferhat

  • 0
    TI__Mastermind 38745 points

    Ferhat,

    The noise you are seeing looks to be mains interference. This problem is common in biopotential applications. The way to mitigate the issue is through use of the RLD feedback loop. This app note has some details about that idea.

    Brian

  • 0 in reply to Brian Pisani
    Intellectual 290 points

    Hello Brian

    1. RLD feedback loop solving noise issue. With RLD buffer is enabled from registers.

    2. Connection patient simulator battery negative to my device GND improve performance.

    3. Also connection 2.43V reference to patient simulator RL port  improve performance.

    So its about CMR but we plan to work without RL usage, we prepare hardware with only RA and LA.

    So what do you prefer for us. Maybe we make a filter on cable side.

    I changed Cfilter 4.7n up to 1uF but has no effect.

    Tells datasheet here Cp1 and Cp2 below 20pF but i didnt get it, is it only about 4.7nF how close to IC.

    I also have another problem, I cant get measurement with 500sps. Im getting very very big values rarely. But its not happening with 250sps. 

  • 0 in reply to Ferhat Bayir
    TI__Mastermind 38745 points
    Hello Ferhat,

    Changing Cfilter to 1uF will change the filter cutoff to 40 Hz. This is way too low. Why do you want the cutoff frequency so low? That filter also will not improve the common-mode rejection because the capacitor is differential between the PGA outputs and therefore provides no common-mode rejection.

    Cp signifies an estimate for parasitic capacitance from the board. This is not a capacitor that you should place on your board.

    To only use 2 electrodes, you can simply ac couple the inputs. However, the lack of RL drive will cause CMRR to degrade. Perhaps in that case you can use a digital notch filter to eliminate the mains interference.

    Brian
  • 0 in reply to Brian Pisani
    Intellectual 290 points

    Hello Brian Ac couppling was usefull, thanks for help.

    I have one more problem.

    Im using internal clk 512kHz

    I can monitor signal with 250sps but im getting faulty readings with 500sps like pictures below.

    I use RDATAC, with interrupt activaticg DRDY signal. Im getting same faulty value if i read again, so i think its not about SPI communication.

    Do you have an idea.

  • 0 in reply to Ferhat Bayir
    TI__Mastermind 38745 points

    Hello Ferhat,

    In RDATAC mode, the device will automatically put new data in the output shift register when DRDY asserts. If your previous data read takes too long, new data can interrupt the current sample and corrupt the sample. This explanation makes sense given you only see it when you increase the data rate. To fix this you can do 2 things:

    1. Use STADAC mode and use the RDATA command to retrieve data (not recommended). In this mode, the device does not automatically overwrite the output shift register so it will not corrupt your samples, but you will miss samples if your SPI routine is still not fast enough to read out all the data in time.
    2. Optimize your SPI routine using RDATAC mode. You can simply increase the SPI frequency or decrease the delays between the time that DRDY asserts and you begin reading data, or perhaps a combination of both. This is the most robust way to solve this problem.

    To understand the exact timing issues, you will need to look at the SPI routine for collecting data with the logic analyzer or scope and identify where delays can accumulate in your routine. Remember, not every sample will be corrupted, so not all the collections will be too slow. It may be hard to find a data collection transaction with the logic analyzer where you can actually see this occurring.

    Brian