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DAC34SH84EVM: Clock and Timing clarification.

Part Number: DAC34SH84EVM
Other Parts Discussed in Thread: DAC34SH84, DAC5675A-SP

Hi All,

For one of my designs I need to generate two independent DAC output voltages (with few discrete steps only)  @ 400 MHz and above. Both the outputs should change simultaneously with the DAC clock.

Initially I used a TI 2-Channel DAC EVM thinking that this will give me two outputs which will change simultaneously. But I realized that the Ch1 and Ch2 outputs are 1/2 clock apart as the Input Data interface is LVDS DDR.

After checking the other DACs from TI, I found that the DAC34SH84 is a high speed DAC (1.5 GSPS) with two separate 16 bit LVDS inputs. The Ch1 and Ch2 are time multiplexed DDR (Data Port 1) and similarly the Ch3 and Ch4 are also time multiplexed DDR (Data Port 2 ).

I have three questions now.

1. As there are two separate input data ports in the DAC34SH84 (Ch1 and Ch2 are time multiplexed on Input Data Port 1 and similarly Ch3 and Ch4 are time multiplexed on Input Data Port 2) will I get simultaneous output changes on Ch1 and Ch3 (and similarly on Ch2 and Ch4) ? Will the Ch1 and Ch3 ( similarly Ch2 and Ch4) outputs change with the same edge of the DAC clock ?

2. The data sheet says the rise/fall time for these DAC outputs is 300ps. Will I get the same rise/fall time on the DAC34SH84 EVM outputs ( as the outputs are transformer coupled ) ?

3. Can somebody in TI actually test the DAC34SH84EVM and confirm me the rise/fall time for the EVM outputs ?

  • Jayant,

    We are looking into this.

    Regards,

    Jim

  • Jayant,

    The DAC uses an internal FIFO to guarantee that all input data arrives at the same time to all DAC's. So for your case, you can use any or all of the 4 DAC's. I am checking to see if we have test data that measured the rise and fall times of the DAC. I have been told that the spec in the data sheet is very relaxed. What application is this for?

    Regards,

    Jim

  • Hi Jim,

    My application is for a Satellite Transmitter Design.

    I have already designed and tested my proto- RF system with external Arbitrary Waveform Generator (AWG) from National Instruments (NI). This AWG gives me rise/fall time of 1-2 ns.

    My final design will include two TI DACs (Part No. DAC5675A-SP) which talks about the rise/fall time of 300ps (quite ok for my application).

    Now, before I conclude the "final achievable quality parameters  of the Transmitter output waveform" in front  of the Design Review Team, I need to test the System with an External DAC with 2 channel outputs changing simultaneously and having the rise/fall time better than 300ps.

    I hope that I have answered your question.

    Waiting for your reply on the rise/fall time of the outputs at connectors J7 (IoutA2), J6 (IoutB2), J3 (IoutC2) and J2 (IoutD2) of the DAC34SH84EVM.

  • Jayant,

    Rise and Fall times are strongly influence by the pcb, and if we attempt this measurement on our EVM, it probably will  not match the values you will see on your board . Our design team has suggested that you plan on modeling/measuring with your PCB/load.  Also due to our limited bandwidth, we will not be able to take these measurements any time soon. If you would like, I can send you a loaner EVM to allow you to try this yourself.

    Regards,

    Jim 

  • Hi Jim,

    I am getting the EVM from TI.

    I have the instruments with very high BW to test the rise/fall time.

    I will do the measurements and share the results with you for the EVM.