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DAC37J82: Subclass 1 without SYSREF support

Michael Kolodchak
Prodigy 60 points

Part Number: DAC37J82

Can it be confirmed that the DAC37J82 does work without SYSREF? 

It claims to support Subclass 1 but allows disabling use of SYSREF. Has this operation been confirmed?

Mike

  • 0
    TI__Guru* 91947 points

    Michael,

    In subclass 1 mode, after the JESD link has been established, SYSREF is no longer needed and can be turned off.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 60 points
    Jim,

    Can you clarify? We do not need to synchronize multiple devices and use SYNCB_P/N to allow the DAC to establish K28.5 synchronization. We do not connect SYSREF_P/N at all. You imply that SYSREF_P/N is needed at least initially. For what? As noted in the datasheet. SYSREF_P/N can be unconnected....

    ........................If not used, it is self-biased with 100mV differential at Vcm= 0.5V.

    Thanks,
    Mike
  • 0 in reply to Michael Kolodchak
    TI__Guru* 91947 points

    Michael,

    The digital blocks such as NCO, JESD, clock dist, all need to be reset after they have been configured. This is done by issuing SYSREF pulses. Due to the architecture of the design, the part requires at least 2 pulses of the SYSREF input. See the attached document for more information.

    Regards,

    Jim

    2335.DAC3xJ8x Device Initialization and SYSREF Configuration.pdf

      

  • 0 in reply to jim s
    Prodigy 60 points
    Jim,

    We actually do not use the NCO, and the clocks and PLLs are all locked fine. We are sync'd and can test on K28.5, D21.5 and ILA patterns - both at 6Gb/s or 12Gb/s. We have set Config36 and config94 to NOT use SYSREF pulses. As mention previously, the datasheet says SYSREF may be left unconnected. But it does appear the JESD link is not up.

    Given all this are you saying we must set the DAC to use SYSREF pulses, regardless of the datasheet instructions? And it is impossible to achieve JESD link up without at least some SYSREF pulses under all configurations?

    Thanks,
    Mike
  • 0 in reply to Michael Kolodchak
    TI__Guru* 91947 points

    Mike,

    The JESD state machine and clock divider block can only be reset by the SYSREF signal. This information will be added to the next release of the data sheet and any mentioning of being able to operate without SYSREF will be removed.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 60 points

    Jim,

    Can the SYSREF pulse extend across multiple DACCLK_P rising edges and still be one pulse?

    That is, are the SYSREF transistions important or just SYSREFs value on rising DACCLK_Ps?

    More importantly I assume we can set the "use next single SYSREF pulse" for each of the DAC subsystems and it won't care about the length of the SYSREF pulse?

    Mike 

  • 0 in reply to Michael Kolodchak
    TI__Guru* 91947 points

    Mike,

    The DAC uses the rising edge of SYSREF so the pulse width will not matter as long as it is not shorter than a multi-frame period (per the standard) if you plan on turning it off. If you leave it running, it will have to be the same frequency as the multi-frame clock or an integer divide of this value.

    Regards,

    Jim