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ADS6425 output abmormal

Turbot
Prodigy 70 points
Other Parts Discussed in Thread: ADS6425

After we convert the serial data output from ADS6425 to parrallel, some DataPort(1, 3, 5, ...) output square wave continously. As shown by logic analyzer in http://thumbsnap.com/VQomySEK

When we input a square wave to ADC, we got the output as below.
http://thumbsnap.com/p986MgqU

May you give any suggestion, thanks.

(We use xilinx virtex ml605 to receive the data, and there is a FMC ADC ADAPTER in between)

  • 0
    TI__Mastermind 29220 points

    Hi,

    I would say that there looks to be an issue with the deserialization logic.  Either the timing of the data bits around the DDR bit clock is off as it is getting latched into the FPGA, or the deserialization logic is incorrect.   I wrote the logic to get this data format deserialized in the TSW1200 Capture Card, so i know how many ways there are to get something wrong.  Attached is a sketch of how i do the deserialization in the TSW1200.

    One good debug tool is to use the test pattern features of the ADC itself.  Using the SPI port to write the the ADS6425, there is the option to have the ADC output a known pattern.  One of these is a custom pattern.  I like to set all the bits in the custom pattern to zero except bit 0, and then see if my deserializer has the one in the right spot.  Then i change the custom pattern to put the one in the next bit position, bit 1.  and i look to see if i deserialize that bit into the proper spot.  In this way i move that '1' across the whole sample to see if my deserialization logic is correct. 

    Then i might use a toggle pattern to see if i have all 12 bits from my deserializer going high at the same time, and all 12 going low together.  It is real easy to get a sample 'split' such that on one clock cycle i get bits lsb through n from sample N output at the same cycle with the bits n+1 through msb from sample N+1. 

    I like to use an arithmetic couting pattern (ramp pattern) to really check out that i have the deserialization correct, but ADS6425 doesn't have the ramp pattern.  So i will sometimes use a *very* slow sine wave to make a ramping edge into the ADC.  I can get a *very* slow edge into the ADC through the transformer coupling by not using a very low frequency sine wave, but rather a sine wave that is a few KHz away from the sample clock and let the input sine wave alias down to look like a few KHz.  In other words, if my sample clock is 100MHz, i may input 100.010MHz to get a 10KHz sine wave and i look for the deserialized sample bits to paint out a ramp input.

    Finally, how are you using the frame clock to do your deserialization?  I like to use the frame clock as if it is another data bit of a known data pattern, and use the position of the 0 to 1 transition on frame clock to know where my msb and lsb are on the data pairs.  In fact, be sure to note that the timing of the frame clock to bit clock is just like any other data bit - there is a setup and hold time for the 'bits' of the frame clock relative to the bit clock edges.

    To use the SPI register space of the ADS6425, you would need to code a state machine from your FPGA to control the SPI clock, data and enable bits.  And move a few surface mount zero ohm resistors on the EVM to let the FPGA control the SPI lines.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 70 points

    Hi Richard

    Thank you for your constructive response! Actually, We are using solution from Xilinx's XAPP866. So we use frame clock as a referece pattern to control bit slip of serdser block and use two SDR serdser primitives instead of DDR input register primitive. Could you pls advise on some debug tips according to such setup?

     

     

    Best Regards

    Turbot

  • 0 in reply to Turbot
    TI__Mastermind 29220 points

    Hi,

    I spent some time trying to get the ISERDES/XAPP866 approach to work with the TSW1200, and again i would suggest the same debug methods here also.  Use the custom pattern to test that the deserialization is working properly.

    We did not choose to use the ISERDES approach for a number of reasons.  First, we had much difficulty in trying to get all of the ISERDES used for all of the channels to be reset at *exactly* the same time and then to keep them all in sync while trying to use the state machine to look at the frame clock and bit slip the deserialization boundaries.  As we tried to get this code to work, the reset logic got more and more complicated and i never did get it to fully work for all of our different format devices.  But also this approach was not suited to what we wanted to do with the TSW1200.  The TSW1200 has to be able to accept 1-wire and 2-wire formats with serialization factors of 6, 7, 8, 12, 14 and 16 bits for all the different devices we support, and the ISERDES approach would not handle that cleanly in a single bit file.  Also the use of the clock managers limited our frequency range of operation while we wanted to support from 2Msps to 125Msps.

    So we went with an architecture that relies purely on synchronous logic of just gates and flipflops, once we got the DDR data latched into the device with the IDDR cell and IDELAY cells.

    in any event, i still think a known test pattern will be needed in order to see what the deserialization is doing.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 60 points

    Hello,Richard p

    I ,a chinese postgraduate student.

     I am also working on interfacing the ADS64XXevaluation board with a virtex 4 ,but I have questions to receive the  data from the ADC, when I use the DDR data format through 2-wire mode.I have seen your design's architecture above,I would really appreciate the reference design's source code ,or you give me some other reference designs.

    my emaile (yanlitao122@126.com)

    regards,

    tao

  • 0 in reply to Richard Prentice
    Prodigy 60 points

    Hello,Richard p

    I ,a chinese postgraduate student.

     I am also working on interfacing the ADS64XXevaluation board with a virtex 4 ,but I have questions to receive the  data from the ADC, when I use the DDR data format through 2-wire mode.I have seen your design's architecture above,I would really appreciate the reference design's source code ,or you give me some other reference designs.

    my emaile (yanlitao122@126.com)

    regards,

    tao

  • 0 in reply to Richard Prentice
    Prodigy 20 points

    Hi Richard

    I have gone through your solution which you used on TSW1200. It looks that there are difficulties if we use it on ADS6425. ADS6425 is a four channels 125 MPS 12 bits high speed ADC, so, if our sampling rate is 100Mhz ,  using 12bits format, DDR and two wires configuration, the forward DDR clock will be 12 X 1000 / 2 /2  = 300Mhz . After IDDR register, the SDR clock rate is 300 MHz . According to your suggestions, deserialization is done by FPGA logic, So we need at least 300MHz clocking speed in FPGA fabric. It will be a challenge.

    Could you pls advise more on that? Thanks advance!

     

    Best Regards

    Dawei

  • 0 in reply to Dawei Lu
    TI__Mastermind 29220 points

    Hi,

    Yes, the clocking rate for the deserialization may be an issue.  For our TSW1200, we can handle a 2-wire 16-bit format at 125MHz, which pushes the DDR bit clock rate in our FPGA to 500MHz.

    But this high clock rate can be confined to a regional clock, as there are not so much logic that needs to run at this rate and than after the data is deserialized the data rate for the samples are back to the sample clock rate.   We are not asking for a global clock to run at this rate across the whole FPGA.  In the case of the ADS6425, each channel would need two IDDR cells, and then approximately 28 or 32 flipflops for the deserialization.  If the eight LVDS inputs (plus the ninth LVDS input for the frame clock and the tenth LVDS input for the bit clock) are assigned to inputs in a single bank of I/O that can be served by a regional clock buffer then you might be able to achieve a higher clock rate than otherwise. 

    Also, the logic needed for the deserialization is not deep, so that the logic for the frame clock load pulse and the muxing in front of the parallel deserialized data registers can fit into a single lookup table. (so whatever the max clock rate that the FPGA can support for going from a flip flop in one logic block into the next logic block through the lookup table would become the max rate at which you could clock this deserializer.)

    With an older FPGA than the Virtex4 that is on the TSW1200 i had to once lock the location of the logic blocks to force the flipflops for the deserializer to all be local to each other, but for newer FPGAs as well as newer FPGA design tools i have not had to resort to locking the locations of the logic.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 20 points

    Hi Richard

    Thank you for your suggestion! For your 2-wire 16-bit case, May I have your UCF file which is including location and timing constrains. And, May I have your clocking scheme especially on relationship betwen IDDR clock, deserial shift register clock and parallel data latch clock?

     

     

    Best Regards

    Dawei