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DAC3164: Config register operation

radar
Expert 3530 points
Part Number: DAC3164
Other Parts Discussed in Thread: DAC3161, DAC3174

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Champs- got a customer who is bringing a board up and we have a few questions-

     1.  The config20 register allows setting allows the DAC output to be set to a static value. I expected that the static value would be output on both channels of the DAC. However, the behavior I am seeing is that the “sifdac” value is only output on channel A and channel B outputs 0V differential. I don’t know if this is expected or if I am misconfiguring something. Can you confirm that this is the expected behavior?

2.       The config3 register allows adjustment of the LVDS clock and data delays. Based on my experimentation, it appears that the DAC3164 uses only the ‘datadlya’ and ‘clkdlyb’ fields. The ‘datadlyb’ and ‘clkdlya’ fields do not appear to have any effect. Can you confirm whether this is the case?

 

Thanks in advance!

  • 0
    TI__Mastermind 29220 points

    Hi,

    I would not expect the sifdac value to only be available on channel A output.  I would expect to see that value on both channels.  I would double check the values you have to all the different portions of the register map to make sure your settings don't have something unexpected like clock for channel B disabled, or a bit set for one channel operation with the other channel put to sleep, or something like that. 

    For the delay fields, take a look at figure 67 of the DAC3161 datasheet.   That is a datasheet for just the single channel version of the device but the datasheet has been updated more recently and the figures were brought more up to date.  The DAC3164 datasheet will be updated in a similar manner.  All four of the delay fields are used.  The 14 bit bus (well, really only 12 bit for the DAC3164 but the core design was the 14b DAC3174) can be split up into two 7 bit busses for the two channels each with its own clock if desired.  So the datadlya and the datadlyb are each responsible for 7 bits of the data bus.   normally these two fields would be set to the same delay value as each other.  it would be unusual to delay half the bus by one amount and the other half by a different amount.  but you could.    And there is the clkdlyb field which delays the dataclock.   That leaves clkdlya which is the delay setting for the SYNC input.    Normally the SYNC input is latched with the DATACLK along with the DATA so that clkdlya would be set to the same value as datadlyb and datadlyb.    so either you would delay the DATACLK with clkdlyb *or* you would delay the data and the SYNC with datadlya, datadlyb, and clkdlya.      Delaying both clock and data would not accomplish much.

    What makes the delay field associated with the SYNC input so confusing is that on the 14bit device, when the data but is split into two 7 bit busses, then it is possible to have a separate clock for each 7 bit bus.  To get the second DATACLK, the SYNC pin is robbed and re-purposed as the other clock input.  That is why the delay field for the input is called clkdlya rather than syncdly or something like that.    But with the 12bit DAC3164 you are looking at, the split bus option is not allowed, and only the confusion remains of why the name for the delay field for the sync input is what it is.

    Regards,

    Richard P.