• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 538 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TSW40RF80EVM: DAC38RF80 external clock and sysref setup and hold time.

guy vaisman
Prodigy 230 points
Part Number: TSW40RF80EVM
Other Parts Discussed in Thread: DAC38RF80

Hi,

I recently purchased and received  TSW40RF80EVM (together with TSW14J56).

A couple of issues:

- There is no BOM, schematics or gerber files online. Could you provide these for a design reference?

- I would like to use the DAC38RF80 without the internal synthesizer, feeding directly with a high speed clock ( >6GHz)
  How can i be sure that i'm meeting the sysref to devclk setup and hold time? the data sheet mentions a sysref capture circuit, 
  can i use this option with the  TSW40RF80EVM?
  Is there a test point i can use to probe sysref and device clock with a scope? ( the IC has a heat sink on top it, so there is no space to place a probe)

Best Regards,

Guy.

 

  • 0
    TI__Genius 9695 points

    Hi Guy,

    I have uploaded the design files to this link:

    Regarding SYSREF to Device clock setup and hold times, this is only important if you need to achieve fixed latency from DAC. Not meeting setup and hold times will only cause your system latency to vary after each power cycle.

    If fixed latency is a design goal, then in DAC38RF80 datasheet, section 8.3.10, there is a description of how the internal SYSREF capture circuit can be used to capture SYSREF reliably. Take a look at this and we are also developing an application note on this featurte that we can share with you when complete.

    Thanks,

    Eben.