Part Number: ADS42LB69
Hello,
We started testing the ADC output to FPGA Interface and observed the following:
1) The ADC was configured to send out all 1s and 0s and the FPGA read them correctly.
2) Then we tried the alternating pattern (register value 0x33) but we get alternate 0xFFFF and 0x0000 (some realignment of data is occurring)
3) We tried the deskew pattern (0xAAAA), instead 0x5555 is being received
4) 8-point sine wave: periodic values with period 8 are being received but all are incorrect.
The problem is that we are not getting the correct data, so there is some data alignment issue.
There is no problem of noise/timing in our opinion because the numbers do not change with time (we acquire data in snapshots of 1024 words at a time) and have done many runs
We are interfacing this to a Xilinx 7 FPGA and the signal flow inside the FPGA is as follows:
1) data goes to IBUFDS and then IDDR (we tried different configurations for the IDDR (opposite_edge, same_edge and same_edge_pipelined), the results are similar (all of them give incorrect values)
2) clock goes to IBUFDS and then IBUFG (the adc_bit_clk_bufds_bufg is used as the clock source for the IDDR)
The data bit clock has been put under timing constraints.
The register configuration for the ADC is:
Hard reset the IC and then,
1) Writing 0x01 to 0x15 (enabling DDR mode)
2) 0x03 to 0x0F (setting the ADC to send test pattern data)
Are we missing anything in the register settings?
Thank you for your time in helping us out,
Regards,
SM
