DAC3484: Maximum fDATA

Hello,

     We need to run each digital channel of the DAC3484 at 200MSps (i.e., between the FPGA and DAC) with the interface being word wide mode (i.e., one sample each for the 4 DAC channels is sent in two clock cycles of the data clock). This leads to running the LVDS interface (fDATA) between the FPGA and DAC at 400MSps (two clock cycles carry 4 samples on both rising and falling edges (DDR-LVDS).

The datasheet on Pg 15 says that fDATA is max 312.5MSps. Is this per channel or is to for the total interface? 

If we look at the datasheet of the DAC3482 (2 channel version instead of 4) then on Pg 15 it is mentioned that the max fDATA is 625MSps in word wide mode and 312.5 in byte wide mode. 

Please advise and thank you for helping us out,

Regards,

SM