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ADS8568: ADS8568 wake up issue

Nir Flysher
Expert 3367 points
Part Number: ADS8568


Dear Team,

My customer is having 2 ADS8568 chips on board on top and bottom on a few cm distance from their FPGA.

They are reporting that once every few power ups the ADC is waking up in a state where it's internal Vref is very close to zero resulting wrong readouts.

They are using the internal Vref.

The phenomena is very hard to duplicate but is still occurring from time to time.

The two ADCs are configured to the exact same configuration using the same commands.

Even if the customer does not configure the ADC and work in the default mode - this phenomena still occurs.

In addition the phenomena always occurring in the same (bottom) ADC. They have assembled 4 boards and the phenomena is consistent across all the four boards.

Do you know of any such issue with the ADS8568 ?

Can you help us debugging this ?

Can this be occurred maybe due to slow/fast slew rates of the VCC ?

Best regards,

Nir

  • 0
    TI__Intellectual 1205 points
    Nir:

    Because there are two ADS8568's in your design, and consistently only the one on the bottom of your PCB is giving you trouble, I would suggest taking a close look at the layout, including decoupling of the supplies.

    Would you be able to send partial schematics and layouts?

    Thank you!
  • 0 in reply to Bryan McKay
    Prodigy 30 points
    An update:
    We had a delay added in the FPGA's FW, so we're configuring the ADC only about 1sec after Power-Up. with this FW the problem doesn't repeat it self.

    that brings up few questions:

    1. is there any importance for the power-up sequence (between the HVDD,HVSS,AVDD,DVDD) ?

    2. what is the wake-up time for the device, after suplly setling ? is it counted from the setling of the AVDD or the DVDD ? or the earlyer between them?

    gil
  • 0 in reply to Gil Glass
    TI__Mastermind 25030 points

    Hello Gil,
    I am glad Bryan was able to help with this. To answer your follow up questions:

    1. There is generally no specific requirement for power up sequence, but when HVDD is supplied before AVDD the internal electrosatic discharge structure conducts, this increases the IHVDD beyond the specified value until AVDD is applied. Overall, it would be good practice to have HVDD and HVSS ramp up after AVDD.
    2. If I were to prioritize the two power supplies, I would prioritizeAVDD. AVDD supplies the internal circuitry, without it, the device does not function. DVDD is only used to drive the digitial I/O buffers, whch means if this is not settled while the device is already operating, you may see correct communications but it will not be clean nor at correct voltages.

    If you are looking at the auto-sleep mode of the device, it requires 10ms for the internal circuitry to active and settle to be able to start a convertion.

    Regards, Cynthia

  • 0 in reply to Cynthia
    Prodigy 30 points

    hey,

    thanks for replying.

    about the wake-up time - the 10ms of sleep mode , is after the first wake up and configuration of the device. i'm refering more to the first time the device is waking-up , after power up. i guess there's a booting process which doesn't accoure when exiting sleep mode.

    so , i'll clarify my question to the wake-up time that is measured since supplies are settled until i can first approach the device. 

    gil

  • 0 in reply to Gil Glass
    TI__Intellectual 1205 points
    Hello, Gil:

    For further clarification, the 10ms that Cynthia mentioned applies to recovering from Auto-Sleep mode, Standby mode, or a Power-On Reset. So for initial power-up of the device, the 10ms would still apply. However, that 10ms only starts when the AVDD is up to the minimum level of about 1.2V.

    In your design, with two ADS8568's on opposite sides of the board, it might be possible for each one to see AVDD coming up at different times.
  • 0 in reply to Bryan McKay
    Prodigy 30 points

    hey,

    thanks for your answears.

    after more measurment, this thread seems "clean".

    it takse about 1 sec since power supllies are stabled until the FPGA addresses the ADC for the first time.

    i'm open for suggestions if you have ideas for tests and measurment to be taken as for what causes this problem.

    best regurds

    gil

  • 0 in reply to Gil Glass
    TI__Expert 3367 points
    Dear Gil,
    What do you mean by "clean" ?
    Does a short delay between the time the FPGA loads to the time you configure the ADC solves the issue ?

    Best regards,
    Nir.