Part Number: ADS52J90
Dear,
We intend to use the ADS52J90 to sample the analog outputs of a custom CMOS image sensor (CIS). Depending on the pixel rate (going up to 100 Mpixels/s per channel), the sensor's SNR perfectly matches the ADC ENOB, which makes this ADC the perfect choice for our application. However, the datasheet leaves us with some questions:
- The CIS analog output will look like of square wave output. Meaning, for each pixel at the output steps and settles to a different value. As such, the input bandwidth of the ADC should be a multiple of the pixel rate. The datasheet's “Recommended Operation Conditions” section, lists Fin= 0 tot 70MHz. The sections about “Analog Input Sampling Network” suggests the input bandwidth is much higher. So our question: What is the actual input bandwidth? Does it very wth respect to sample rate?
- Additionally, the track&hold operation is not clear:
- When looking at comparable ADC's, some of them allow analog tracking only during half the sample clock period. Obviously, this will also impact the input bandwidth requirement. The datasheet mentions odd/even sampling. Does this mean the tracking window is one full sample clock cycle? The aperture delay is reported in the datasheet, but the aperture opening is not clear...
- Related to the above: when can the analog output start to change, aka transition to the next pixel value? This defines our phase delay between sample clock and CIS pixel clock. Figure 58 in the datasheet depicts tx as the falling edge of the sampling clock, being the end of the tracking. Is it safe to assume the distance between the latter and the external System Clock is the aperture delay? Apart form CIS internal propagation delay, is this the only ADC-related delay to take into account?
Best regards,
Joel Neys
