Other Parts Discussed in Thread: DAC3482
Hello,
We are facing an issue of synchronization loss, the details are as follows:
WORKING CASE:
1) DATACLK is set at 250MHz, Sync source is SYNC (SYNC is at FSYNC/16) word wide interface: The DAC is being supplied a 1GHz clock and the device set for 8x interpolation.
In this case when the clkdiv_sync is disabled (as advised in the datasheet) to check the stability of the clocks, the DAC continues to remain synchronized.
NON-WORKING CASE:
2) DATACLK is set at 400MHz, Sync source is SYNC(SYNC is at FSYNC/16) word wide interface: The DAC is supplied a 200MHz clock and set for no interpolation.
In this case when the clkdiv_sync is disabled the synchronization is lost. When clkdiv_sync is enabled we see the correct output from the DAC (a single tone is being sent and we see it on a spectrum analyzer). The signal is solid and the spurious are reasonable.
The overall clock generation on the board is being done by a good quality clock generation chip. This chip supplies the DACCLK (which in the two cases is 1GHz and 200MHz resp.) and also supplies the reference clock to the FPGA. A PLL inside the FPGA uses this clock to generate DATACLK & SYNC.
Thank you for looking into our case,
Regards,
SM
