• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 695 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC32RF45: ADC32RF45 data format and DDC operation

John Dusatko
Prodigy 150 points
Part Number: ADC32RF45
Other Parts Discussed in Thread: DAC38J84

Hello,

I am trying to understand the data format of the ADC and mathematics and the DDC mixer operation:

The first part of my question is: What format is the raw 14-bit ADC data (when running the device in bypass mode) in? Is it two’s complement or offset binary? I cannot find any references to the data format in the ADC32RF45 datasheet. Along these same lines, if I use the DDC block, what is the data format of the resulting 16-bit I and Q data at the block outputs (and gets sent across the JESD link)? The DAC38J84 datasheet spells out the data format as well as offers a control bit to select between 2’s comp and offset binary, does the ADC32RF45 have something similar?

The second part of my question has to do with the mathematics of the complex mixer inside of the DDC block. How is this implemented? So the ADC data is 14-bits while, and (according to the datasheet) the NCO output word width is 16-bits. Presumably the logic must do a sign extension on the ADC data to match widths; additionally if one multiples two n-bit quantities the resulting product will be n+n bits. Since the DDC block output is only 16-bits, I am wondering how multiply operation is actually accomplished both mathematically as well as pictorially; i.e. is the complex mixer the same structure as that of fig.70 in the DAC38J84 datasheet?

Thanks and Regards,

John

  • 0
    TI__Mastermind 29220 points

    Hi,


    The ADC32RF45 does not have a SPI register bit to select between the Offset Binary format or 2's complement format.   The format is fixed, and is 2's complement I believe.   The difference between the two formats is only in the most significant bit of the sample.  If you have offset binary and you invert the most significant bit then the sample becomes 2's complement.  if you invert the MSB again then the sample is turned back to offset binary.

    I don't know the exact block diagram of the filter and arithmetic blocks of the DDC functions.  The data from the ADC front end is 14 bit, but the resulting 16bit output samples are due to the decimation *filter* block.  If the decimation filter in say a decimate by 4 example were simply throwing away three out of four samples, then it would not be a filter at all but just decimation, and the 14 bit samples in would still be 14 bit samples out.  But the filter *is* using all of the samples in the process, so in a way a decimation by 4 filter is kind of analogous to an averaging by four function, where four 14bit samples averaged together would require 16 bits to represent without losing precision.   That is essentially where the 16 bit resolution comes from out of the decimation filter block.   I do not know the internal resolutions of the paths inside the complex mixer block.

    Regards,


    Richard P.