Hi,
We are using DAC3482 in our desgin, an FPGA is used to drive the data samples to the DAC. DAC configuration is given below:
Fout = 70 MHz
DATA CLK = 480 MHz
DAC CLOCK = 960 MHz
Interpolation factor = 2x
With these configurations, we are observing some Spuriouses at Fout +/- 20 MHz which are at around 60 dBc below the required signal level. When we plot the data going out of FPGA to wards DAC, here we are seeing these components at around 95 dBc below the required signal power. But looks loke these Spuriouses are getting boosted by around 30 DB at the DAC output. Are there any other parameters which could cause this? Please help us in resolving this issue.
With this thread, we have Attached a ZIP file containing the FPGA DATA samples (in 2's complement form, 16bit @480 MHz), a snapshot of Plot of the FPGA data samples, DAC register configuration details and a snapshot of actual DAC output plot in SA.
Thanks,
Kiran