ADC32RF45EVM: Configuring JESD204B settings

Hi,

In the Overview section 8.1 of the detailed description is the statement that each channel is 4-way interleaved.  "Each ADC channel is internally interleaved four times and equipped with background, analog and digital, and interleaving correction."    Also in the block diagram on that page and on the front page of the datasheet is an indication that each channel has a block labeled ADC that is stacked four deep.  But this is simply how the ADC is able to achieve a sample rate of as much as 3Gsps.  Once the four sub-ADCs are interleaved and the samples are digitally corrected for offset mismatches between the four sub-ADCs the data stream simply looks like samples from an ADC operating at a sample rate of as much as 3Gsps.  This is unrelated to the operation of the DDC blocks.

If you look at the bypass mode of operation such as the LMFS=82820 mode, the DDC blocks are bypassed and the 'M' in the LMFS is 2 because it is a 2 channel device.     If you were to enable the DDC blocks but were to only enable one DDC for each channel and choose Real output, then M would still be 2 as there would still just be the two streams of data from the device.    But since each channel can have two DDCs enabled, with each DDC block getting the same data into the DDC from the ADC block, it can make it look like there are four 'ADCs' operating and thus M could be 4.   Or, each DDC block could be outputting I and Q data streams which also makes it appear that there are more 'ADCs' operating.   If each channel had two DDCs enabled in complex mode, then you see LMFS modes such as LMFS=8821 where M is 8 in this mode.   The FPGA receiving the data stream sees 8 distinct data streams even though there are still only two front end ADCs creating the data streams.  Figure 76 shows an example of one channel ADC being fed to two DDC blocks where each DDC block is decimating and the NCOs chosen to output two different bands of the spectrum.   To the FPGA receiving the data it would the same as two completely separate ADCs sampling the data and outputting the respective bands of the spectrum.

Enabling two DDCs per channel increased the amount of data that must be conveyed across the JESD204b link from the device to the FPGA.   But as the decimation factor increases the amount of data that must be transmitted is decreasing.  So you can see in the tables 16 through 23 you can see that with higher decimation factors that there are numerous choices of mode that only need to use two lanes if one DDC is enabled per channel.   But if two DDCs are enabled per channel then there are numerous modes of operation that can get by with 4 lanes, and others that require all 8. 

But if you want to see all of the spectrum up to Nyquist, then the DDC modes would not be what you want.  If your sample rate were 1.5Gsps, then Nyquist would be 750MHz.  If you want to actually *see* all of that 750MHz bandwidth you would have to choose Bypass.   If somewhere in that 750MHz is a smaller bandwidth of interest (such as maybe a 20MHz wide bandwidth that has been modulated up to a higher carrier frequency) then you can use the decimation mode to narrow down the bandwidth that is transmitted to only that which is of interest to you and use the NCO to locate that narrowed down portion of the spectrum to catch the signal of interest.  There are numerous decimation modes that would utilize 2 lanes, or 4, or 8.   But the Bypass mode requires all 8 in order to get the data across the link.

That is why I mentioned the ADC32RF42.   It looks like an 'RF45 that has be 'cut in half'.  Still two channel, but with a range of sample rate that is halved, and using half as many lanes in bypass mode.  But you mention 400 Msps - if you were to operate the ADC32RF45 at 1.6Gsps and choose a decimation by 4 mode, then the data stream is cut down to 400Msps and you would be able to use only four lanes.   You would use LMFS=4421 if you wanted complex output from the DDC blocks (table 16) or maybe LMFS=4211 if you wanted real output from the DDC blocks (table 20).

Regards,

Richard P.