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ADS5263: driving circuit

Anton Fortunatov
Prodigy 80 points
Part Number: ADS5263

Hello!

We are using ADA4930 to drive ADS5263. Maximum slew rate of the signal at the input of ADC is 47V/us. Acquisition Time should be ~85ns. Here is a fragment of the circuit:

Are there any mistakes in our design? I'm confused by the phrase in ADS5263's datasheet (page 63): "A 5-Ω to 15-Ω resistor in series with each input pin is recommended to damp out ringing caused by package parasitics. It is also necessary to present low impedance(<50Ω) for the common mode switching currents. This can be achieved by using two resistors from each input terminated to the common mode voltage (VCM)."

1) Why do we what to place those 5-Ω to 15-Ω resistors in series with each input? I think we need a little a possible impedance between "reservoir" capacitor C5/C7 and sampling circuit of ADC.

2) Could you explain why I need "two resistors from each input terminated to the common mode voltage"? 

Another question is about analog input equivalent circuit (figure 90 page 62). I'd like to simulate glitches caused by sampling circuit.

3) What are timing diagrams of those three switches? Sampling switches are "off" during convertion period and they are "on" rest of the time. Right? What is timing diagram of the third switch (rightmost)?

Thank you!

  • 0
    TI__Mastermind 18285 points
    Anton,

    Thank you for your interest in TI parts. We have assigned your post to the correct applications engineer and we should have a response soon.
  • 0
    Prodigy 80 points

    Something wrong with schematic attached to my first post. Another try:

  • 0 in reply to Anton Fortunatov
    TI__Expert 4145 points

    Hi Anton,

    Figure 103 in the datasheet depicts what the datasheet means for question 2--it likely applies only when adding a common-mode voltage signal an AC-coupled input. Since you are DC-coupling your amplifier output to the ADC input, you just need to make sure the Vcm is as specified in the datasheet.
    The 5-15ohm input resistances are fairly small and recommended to reduce ringing if present.

    I believe all three switches are on when charging the sampling capacitors during sampling/acquisition only but I'll have to confirm with my IC design team. I'll get a response back to you by the end of next week.

    Sincerely,
    Olu

  • 0 in reply to Olu Sodipe
    Prodigy 80 points

    Hi Olu,

    Any updates on ADC's input circuit model and switch timing diagram? We still have large glitches and I what to play with driving circuit parameters.

    What topology of driving circuit is better: a) have two capacitors from ADC +in to GND and -in to ground

    or

    b) have one capacitor between ADC +in and -in as shown in my circuit above?

    Another question is input clock. The eval board datasheet (slau344a.pdf) says we can use ether sine input clock filtered with narrowband filter or normal meander clock. What option is recommended for precision low noise design?

  • 0 in reply to Anton Fortunatov
    TI__Expert 4145 points

    Hi Anton,

    All we have for the ADS5263 is the IBIS model as shown on the product page.

    I can confirm that all three switches come on at the same time when charging the sampling capacitors as I mentioned earlier.

    If you are supplying an external Vcm to the ADS5263, make sure it is approximately 1.5V +/-50mV as specified here.

    Regarding the capacitors, two capacitors likely better as the circuit would then be able to provide common-mode charge compensation in addition to differential charge compensation.

    Either clock option is fine but the LVPECL clock edge might be slightly better for the device.

    Sincerely,

    Olu

  • 0 in reply to Olu Sodipe
    Prodigy 80 points

    We are using internal VCM (register 0x42 is 80, pin INT/EXT #56 is pulled to GND).

    Falling edge of the CLK_P cause all three switches to close (turn on), and rising edge of the CLK_P cause all three switches to open (turn off). Right? Delay between posedge CLK_P and switch opening is t_a<3ns (aperture delay). What is delay between negedge of CLK_P and switch closing? Our glitches are delayed from negedge of CLK_P for ~20ns.  Can those 20ns be the delay between negedge of CLK_P and switch closing?  There is no reset switch, so charges at the sampling capacitors remain between samples?

    Wouldn't those capacitors from +in and -in to GND be a path for common mode noises from the ground? Those capacitors will be a little bit different (2% tolerance at best). Wouldn't it skew differential operation of the circuit?

    Does ADS5263's IBIS model correctly simulate analog input circuit and its transients? Does macromodel of ADS5263 exist?

    Is it possible to get ADS5263 evaluation board design files in order to carefully study its layout?

    Thanks!

  • 0 in reply to Olu Sodipe
    Prodigy 80 points

    Olu, please respond to previous post. We still need your help. Here are our waveforms at ADS5263's input with constant signal.

    single ended measurement (IN3A_P):

    below is differential mesurement IN3A_P-IN3A_M:

    This is VCM output pin (ADC is internal VCM mode):

    So we have both common mode and differential glitches.

  • 0 in reply to Anton Fortunatov
    TI__Expert 4145 points
    Hi Anton,

    The IBIS and SPICE models will likely not help you simulate sampling glitches as they are generally used to verify output interfaces and effects of transistor variation respectively.

    Unfortunately, we also cannot provide the design files for the EVM.

    It looks like your amplifier has sufficient BW to keep up with the sampling action of the ADC--is that your sampling clock there at 10MHz? Also can you provide a scope capture of the INM pin?

    You can also use the GLOBAL PDN register setting (register F) or the PDN pin to power down the ADC portion of the IC in order to make sure it is not noise coupling from somewhere else on your board.

    Sincerely,
    Olu
  • 0 in reply to Olu Sodipe
    Prodigy 80 points

    great idea! thank you! we will measure traces with powered down ADC.

    Input clock is 10MHz (green trace on my images). I think glitches do caused by ADC because one of glitches is shifted against negative edge of the input clock by ~20ns. Is it the moment when all three switches in ADC's input circuit close (turn on)?

    Please note that input signal is constant, so sampling capacitors are charged at this voltage and I don't expect any glitches at all.

    Here is INM trace:

  • 0 in reply to Anton Fortunatov
    TI__Genius 12025 points

    Hi Anton,

    How are you?

    Thanks for using our ADS5263 device.

    Yes, according to your description of setting internal Vcm mode (shown as below):

    Could you please double check and make sure whether you have the following register settings:

    Thank you!

    1) Please set register as Address=0xF0, Data=0x0000

    2) Please set register as Address=0x42, Data=0x8000

    3) Please make sure this pin: INT/EXTZ is tied to Logic High.

    4) Then please measure Vcm output voltage would be around 1.5Vdc.

    And see if this could help or not.

    Thank you very much.

    Have a nice day!

    Best regards,

    Chen