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ADS4145 Low speed operation

Arvind Bhat
Prodigy 235 points
Other Parts Discussed in Thread: ADS4145

I am planning to use the ADS4145 in low speed operation (<20Msps). I had a concern regarding this. The datasheet recommends using this part with CMOS interface at low sampling speeds for lower power and better setup/ hold times. 

For our application, this ADC will interface with an FPGA tied to 2.5V bank voltage, and i cannot change this bank voltage. The 1.8V CMOS interface from the ADS4145 will marginally make the Vih requirements. So i wanted to check if there are performance issues in using this part in LVDS mode for low sampling speeds ? Will the part provide good SNR, SFDR or is there significant degradation ?

Thanks,

AB

  • 0
    TI__Mastermind 44680 points

    Hi Arvind

    Section 7.18 of the product datasheet shows the device SFDR and SNR performance for LVDS interface mode at clock rates down to 20 MHz.

    I expect you will achieve adequate performance as long as your input frequencies aren't too high. You can see that for high frequency inputs (above around 100 MHz) better performance is achieved at higher clock rates.

    Best regards,

    Jim B