TSW14J56 EVM, D8 MEM FAIL status

Hi Kiman,

You are correct. If LED D8 becomes illuminated, it means that there is a DRAM issue. (Just to be clear, you are able to connect to HSDC Pro, but error happens when you try to capture?)

Unfortunately, the board must be replaced. Please return it to TI through your appropriate channels. Before you return the board, could you please provide the serial number that is associated with the board when connecting to HSDC Pro? Thank you!

Regards,

Dan

Kiman,

All applogies, but please do not return the board yet. I need  to revisit this issue, as it appears I was incorrect in my initial diagnosis. I will replicate your setup in the lab, and see if I get similar results.

Thanks for your patience.

Dan

Hi Kiman,

I was able to get the ADS54J66 to capture by using the quick start section of the user's guide. Please ensure that you follow these steps, as written, in order to prove that the hardware is functional. Also, please ensure that the ADS54J66 power supply can supply more than 1A (mine draws around 1.3 amps after configuration files are loaded).

After making all connections and loading HSDC Pro firmware and ADS54J66 configuration files (as shown in quick start guide), your setup should look like the picture below.

After entering ADC Data Rate and clicking "Capture", your setup should look like this. Notice that D3 on ADS54J66 illuminates after loading the first configuration file in the ADS54J66 GUI.

Notice that D3 has extinguished and D4 is now flashing. HSDC Pro should have a capture that looks something like this.

Could you please tell me (or screenshot) what error HSDC Pro is giving you?

Regards,

Dan

Kiman,

From your photo, it looks like you have an early version of the ADS54J66EVM because the ADC device is labeled as a pre-production unit. Send us your address and we will get you an updated EVM ASAP.

Regards,

Jim

Hi Dan and Jim,

I found one of missing that was ADC output data rate unit wrong. I did not typed 'M' MHz unit.

After correction the FFT mode looks good.

But Codes (Amplitude) mode has offset maybe not correctly decoded sign bit.

Jim, please send ADS54J60EVM production version I'd like to compare with my pre-production ADC board.

I have some test result with my own zynq706 FPGA board and had one issue at the time domain, I'd like to compare two ADC board characteristic.

Thanks a lot for your support.

Kiman

Hi Jim,

I received the new board and confirmed with our beam signal.

Thank you so much for send a new board.

One of issue is channel to channel phase are not same.

For example CH1 and CH3 are same phase, CH2 and CH4 are same phase.

But CH1 and CH2 are 180 degree phase difference. This issue coming from ADS54J66 EVM board.

Test condition:

Rf input 499.680 MHz

ADC Fs = 499.680 MHz  Sync with RF input

ADC internal mode 8 which is burst mode.

Thanks,

Kiman

Kiman,

To make the routing of the analog traces symmetrical and keep everything on the top side of the board, we swapped the P and N signals of channels 1 and 3 going to the ADC. This is why you are seeing what you are.

Regards,

Jim 

Hi Jim,

Ok got it that's why!

As I mentioned before about our setup:

RF Fin = 499.680 MHz

ADC sampling  Fs = 499.680 MHz

We assume that Fs clock edge is Rf input positive peek value (we used phase shift for finding peak value).

Some reason I observed internal ADCs has different offset values, each channel has two ADCs and sampling rate is Fs/2.

This offset difference is coming from our setup or noise coupling ?

If you have any experience please advice me.