Other Parts Discussed in Thread: LMK04828, ADS54J54
I'm connecting the ADS54j54evm to a Xilinx FPGA evaluation board through an FMC connector. I'm observing some strange behavior when I test the ADC. Here is the background:
- I am using a sample rate of 500 Msps, and two lanes. LMFS=8411
- I can receive the test patterns (incrementing pattern or alternating pattern) across both lanes without issue.
- I then input a 10 MHz, 0 dBm sine wave into the ADC and observe the output inside the FPGA. The FPGA has a Xilinx JESD204b core in the design to do the decoding. The upper lane that represents bits 13:6 of the input signal look good. The lower lane with bit 5:0 is random data. It's not a good signal -- the FPGA decode is showing errors on that lane.
- If I change the frequency or amplitude of the sine wave, the good lane will go bad as well. The only way to recover is to assert "sync" to the ADC, and then the one MSB lane does recover.
At this point I am stuck and can't figure out the source of the problem. This could be a problem in the FPGA, but it's hard to determine at this point and I can use some guidance. Here are some other steps that I tried that will be helpful.
- I have replicated this exact behavior on our own hardware, which has the same ADC and FPGA on the same board. So this rules out a hardware problem.
- I've tried both using a continuous and a pulse-based SYSREF on the EVM, which made no difference.
- I changed the configuration of the hardware to use a single lane. In that case, the lane works for about 1000 clock cycles, followed by bad random data.
Any help would be greatly appreciated. If you need any more information, please contact me.