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ADS131E08: DRDY signal stability question

Part Number: ADS131E08

 I am planning to utilize the ADS131E08 as the front-end for an inertial navigation system and am wondering about the stability of the DRDY signal. Is there a specification buried within the documentation that will tell me the worst-case jitter on the signal that I can expect? I plan to be reading 3 gyroscopes and 3 accelerometers in Continuous Conversion Mode and I am hoping that the DRDY interrupt signal is stable enough to be used to drive the discrete time domain calculations.

Any insights into what can cause variations in the absolute timing of the DRDY signal will be greatly appreciated.

Cheers,

-Steve

  • Hi Steven,

    The DRDY output of the ADS131E08 is basically controlled by the master clock.  Please review section 9.4.1.1 of the datasheet for some detail on how the DRDY signal behaves based on settling time and data rate.   The latency of DRDY is based on tUPDATE, which is 4/fclk.

  • Thank you Tom,
    I have studied section 9.4.1.1 but it does not mention anything about variations in the timing of a pulse stream of DRDY from the RDATAC mode.
    Is there anything that will cause DRDY to slightly vary in timing from assertion to assertion?
    Thanks,
    -Steve
  • Hi Steve,

    The digital filter inside the ADS131E08 provides a fixed data rate output based on the settings you program into the various registers, so unless you change the master clock speed or modify the data rate, the DRDY signal will remain constant. Referring to Figure 33, the first instance of DRDY from START is the settling time of the filter, from there on out, the falling edge of DRDY will be at the Data Rate you define with the DR[2:0] bits in the CONFIG1. Since the data rate is fixed based on the master clock, there may be some minor variations in frequency over temperature - you can review the Electrical Characteristics table for details when using the internal oscillator.