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ADS1298 system with Right Leg Driver multiple chips, 1 chip generates reference 3.0v system, High Resolution, 10K samples per second useable

josh wojnas
Intellectual 805 points
Other Parts Discussed in Thread: ADS1298

ADS1298 system with Right Leg Driver multiple chips, 1 chip generates reference 3.0v system, High Resolution, 10K samples per second useable...

 

What I am trying to do now is set the registers for the ads1298 by using a xilinx FPGA. I want to set the clk in the fpga to the clk to the ads1298 for 10ksps or maby higher in the fpga and divide it down for the ads1298.

Then the SCLK should be clk/4=sclk so loading the registers their is not a delay.

I know I am interested in a system with 10K SPS their will be multiple chips with a shared voltage reference created by one of the chips. They should all be set to High Resolution the systems should run at 3v. The Right leg driver multiple chip option would be used as shown how multiple chips can have 1 DRL then before that how the DRL circuit is configured.

So how would you sugjest how the registers should be set? The ones with the defalts allready ok.

What pages on the data sheet should I refer to?

  • TI__Guru**** 181021 points

    Hi Josh,

    Not sure I understand the question.  Are you referring to the RLD registers themselves or the configuration of the muxed inputs to the RLD block?

  • in reply to Tom Hendrick
    Intellectual 805 points

    Here is what I have done so far I am making a spread sheet of what the registers are as defalt and what I think  should be loaded in eatch of them.

     

     

    .

    		 address regester reset value (DEC) bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit1 BIT 0 LOAD VALUE Main Load Value chain if different REASON read value

    .

    		 DEVICE SETTINGS READ ONLY

    .

    		 0 ID X REV_ID3 REV_ID2 REV_ID1 N/A DEV_ID2 DEV_ID1 NU_CH2 NU_CH1 xx read only xxxx x010

    .

    		 GLOBAL SETTINGS ACROSS CHANELS

    .

    		 1 CONFIG1 6 b1000 001 hi res & 16ksps clk64khz? sclk16khz? b0000 0110

    .

    		 2 CONFIG2 64 b0100 0000 defalt doent match b0

    .

    		 3 CONFIG3 64 b0101 0100 master load... b0100 0000

    .

    		 4 LOFF 0 b0000 0010

    .

    		 CHANNEL SECIFIC SETTINGS

    .

    		 5 CH1SET 0 b0001 0000

    .

    		 6 CH2SET 0 b0001 0000

    .

    		 7 CH3SET 0 b0001 0000

    .

    		 8 CH4SET 0 b0001 0000

    .

    		 9 CH5SET 0 b0001 0000

    .

    		 10 CH6SET 0 b0001 0000

    .

    		 11 CH7SET 0 b0001 0000

    .

    		 12 CH8SET 0 b0001 0000

    .

    		 13 RLD_SENSP 0

    .

    		 14 RLD_SENSN 0

    .

    		 15 LOFF_SENSP 0

    .

    		 16 LOFF_SENSN 0

    .

    		 17 LOFF_FLIP 0

    .

    		 LEAD OFF STATUS REGISTERS

    .

    		 18 LOFF_STATP 0

    .

    		 19 LOFF_STATN 0

    .

    		 GPIO & OTHER

    .

    		 20 GPIO 15

    .

    		 21 ACE 0

    .

    		 22 RESP 0

    .

    		 23 CONFIG4 0

    .

    		 24 WCT1 0

    .

    		 25 WCT2 0
  • in reply to josh wojnas
    Intellectual 805 points

    it seems to have cliped a lot of the info so maby I should make the columns be name, defalt, guess main creates ref v, secondary, defalt read main, defalt read secondary

  • in reply to josh wojnas
    Intellectual 805 points

    Here are my guesses for the register settings based on the data sheet.

    What should the simplest clk and sclk settings for data loading and retreval for 10K samples per second minimum and trying not to go over the next step up.

    The RLD or DRL is used and this is for multiple chips one main and many secondary. The main one could generate the reference voltage but maby it is better for eatch chip to create its own.

     

    address regester reset value (DEC) LOAD VALUE Main Load Value chain if different REASON read value    
    DEVICE SETTINGS READ ONLY                
    0 ID X xx xx read only xxxx x010    
    GLOBAL SETTINGS ACROSS CHANELS                
    1 CONFIG1 6 b1000 001   hi res & 16ksps clk64khz? sclk16khz? b0000 0110    
    2 CONFIG2 64 b0010 0000     b0100 0000    
    3 CONFIG3 64 b1101 1110 b0101 1110 main load secondary also create their own ref b0100 0000    
    4 LOFF 0 b0000 0000     b0000 0000    
    CHANNEL SECIFIC SETTINGS               500SPS
    5 CH1SET 0 b0001 0000     b0000 0000    
    6 CH2SET 0 b0001 0000     b0000 0000    
    7 CH3SET 0 b0001 0000     b0000 0000    
    8 CH4SET 0 b0001 0000     b0000 0000    
    9 CH5SET 0 b0001 0000     b0000 0000    
    10 CH6SET 0 b0001 0000     b0000 0000    
    11 CH7SET 0 b0001 0000     b0000 0000    
    12 CH8SET 0 b0001 0000     b0000 0000    
    13 RLD_SENSP 0 b1111 1111     b1111 1111    
    14 RLD_SENSN 0 b1111 1111     b1111 1111    
    15 LOFF_SENSP 0 b0000 0000     b0000 0000    
    16 LOFF_SENSN 0 b0000 0000     b0000 0000    
    17 LOFF_FLIP 0 b0000 0000     b0000 0000    
    LEAD OFF STATUS REGISTERS                
    18 LOFF_STATP 0     read only b0000 0000    
    19 LOFF_STATN 0     read only b0000 0000    
    GPIO & OTHER                
    20 GPIO 15 b0000 1111     b0000 1111    
    21 PACE 0 b0000 0000     b0000 0000    
    22 RESP 0 b0000 0000     b0000 0000    
    23 CONFIG4 0 b0000 0000     b0000 0000    
    24 WCT1 0 b0000 0000     b0000 0000    
    25 WCT2 0 b0001 0100     b0000 0000    
  • in reply to josh wojnas
    Intellectual 805 points

    I fixed some things this is what I think would be the simplest setup to test the system..

     

     

    address

    regester

    reset value (DEC)

    LOAD VALUE Main

    Load Value chain if different

    REASON

    read value

    DEVICE SETTINGS READ ONLY

    0

    ID

    X

    xx

    xx

    read only

    xxxx x010

    GLOBAL SETTINGS ACROSS CHANELS

    1

    CONFIG1

    6

    b1000 0001

    7=hi-res 2:0=00116ksps clk64khz? sclk16khz?

    b0000 0110

    2

    CONFIG2

    64

    b0000 0010

    1:0 test signal not used

    b0100 0000

    3

    CONFIG3

    64

    b1100 0000

    b1100 0000

    7=en ref buf 2=rld buf en

    b0100 0000

    4

    LOFF

    0

    b0000 0010

    1:0=10 do not use lead off freq?

    b0000 0000

    CHANNEL SECIFIC SETTINGS

    5

    CH1SET

    0

    b0001 0000

    6:4=001 gain =1

    b0000 0000

    6

    CH2SET

    0

    b0001 0000

    6:4=001 gain =1

    b0000 0000

    7

    CH3SET

    0

    b0001 0000

    6:4=001 gain =1

    b0000 0000

    8

    CH4SET

    0

    b0001 0000

    6:4=001 gain =1

    b0000 0000

    9

    CH5SET

    0

    b0001 0000

    6:4=001 gain =1

    b0000 0000

    10

    CH6SET

    0

    b0001 0000

    6:4=001 gain =1

    b0000 0000

    11

    CH7SET

    0

    b0001 0000

    6:4=001 gain =1

    b0000 0000

    12

    CH8SET

    0

    b0001 0000

    6:4=001 gain =1

    b0000 0000

    13

    RLD_SENSP

    0

    b1111 1111

    all bits effect RLD

    b1111 1111

    14

    RLD_SENSN

    0

    b1111 1111

    all bits effect RLD

    b1111 1111

    15

    LOFF_SENSP

    0

    b0000 0000

    off sense detect

    b0000 0000

    16

    LOFF_SENSN

    0

    b0000 0000

    off sense detect

    b0000 0000

    17

    LOFF_FLIP

    0

    b0000 0000

    off sense detect

    b0000 0000

    LEAD OFF STATUS REGISTERS

    18

    LOFF_STATP

    0

    read only

    b0000 0000

    19

    LOFF_STATN

    0

    read only

    b0000 0000

    GPIO & OTHER

    20

    GPIO

    15

    b0000 0000

    all write all 0 out put

    b0000 1111

    21

    PACE

    0

    b0000 0000

    b0000 0000

    22

    RESP

    0

    b0000 0000

    resp circuit off

    b0000 0000

    23

    CONFIG4

    0

    b0000 0000

    b0000 0000

    24

    WCT1

    0

    b0000 0000

    b0000 0000

    25

    WCT2

    0

    b0000 0000

    b0000 0000