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ADS1299: Significant DC-Offset introduced by BIAS (standard configuration)- clipping of EEG electrodes for G >1

Part Number: ADS1299
Other Parts Discussed in Thread: TINA-TI

Dear Community,

after several days of debugging and browsing quite a while through this forum, I was not able to find a solution or answer to this problem (see TITLE), even though the question has been there already. 

I am using the ADS1299 in a hybrid acquisition setup, whereas 6 channels are used for EEG- Acquisition. The ADS1299 circuit was based heavily on the datasheet, application note and evaluation kit schematics - and the developed solution has been in use here for more than a year. The following details might be of interest:

  • quasi-symmetric power supply from a battery (within the allowed range given in the datasheet): AVDD = +2.7V, AVSS = -2.55V, AGND = 0V
  • pcb design as mixed circuit with split analog/digital grounds as recommended, star ground at analog voltage supplies
  • DRL / BIAS feedback resistor/capacitors values are chosen as in the ADS1299 evaluation kit schematics: 1Meg Ohm / 1.5nF
  • EEG AREF and BIAS buffer both use internal reference (AVDD+AVSS)/2 = -75mV (referenced to AGND)
  • single-ended measurement of ch1-6 by using a common electrode to In1-6N (not SRB1, since channels 7-8 are used for another puprose)
  • more in the following excerpt of the schematic

Register Configurations:

  • When bias enabled but not measured: CONF3= b1110 1100
  • When bias measured: CONF3= b1111 1100 and ChnSET bits[2:0]= b010

Now the Problem:

Depending on the configuration of the bias (turned on/off, using different combinations of inputs - BIAS_SENSP/ BIAS_SENSN), the bias signal often shows a significant DC offset, that is inexplicable to me.
When i measure the DC bias signal without with the SENS/N registers 0 (no inverting channel inputs to the bias signal), i measure a negligible dc offset, as expected.

However, when any SENS registers are configured, i get dc offsets in the range up to the Volt-level, which results in clipping of the eeg-channels when Gains>1, in on-body measurements. Trying to investigate this and to give an example, I just the internal ADS1299 test-signal on CH1, set BIAS_SENSP to b0000 0001 and BIAS_SENSN all to 0, and measured the bias signal on CH2. Please see the following screenshots



As expected, the bias signal shows the inverted test-signal (which has a slight negative offset, see ch1) - however with a gain of G=-2.4 and adds an OFFSET of ~1.6V!!

The Gain is roughly the one expected from the TI 10 Applications and Implementation Note on the ADS1299 (Rev. C). here i expect (with Rf=1Meg) and N=1 (Number of Channels used for Bias Drive, here IN1P) a gain of G=3 or (if 220kOhm are used, these are actually the values shown in TI datasheets for the PGA resistors) of G=4.54. 
  

A test for all input gain levels of CH1 (amplifying the test signal with G=1 up to 24) always resulted in a constant amplification of the ac signal (measured gain G=-2.4). The offset remained constant at around 1.6V when using only a single input channel to the Bias stage.

The small difference in gain from the expected one does not matter so much - the huge DC offset does however: With bias-signals  with these dc-offsets on the body, the EEG-electrodes directly clip (for G>1) and I cannot measure a proper signal.
Of course I started evaluating with electrodes on the body - but ended up narrowing down the Problem to everything inside the ADS, to make sure it is not another physical problem of any kind in the external setup.

  • adding channels to the bias can increase the offset up to to AVDD/AVSS
  • The offset does not seem to result from the small dc offset in channel 1 and a huge gain of the DRL circuit. If it was so, the test signal would have to to be amplified with the same gain
  • The dc-offsets do not always have the same levels. When used on the body, (with e.g. CH1 measuring EMG/EOG/EEG) and depending on the configuration of the SENS registers,the offsets can be also in the range of x*100mV.

Thank you very much on any notes and thoughts on this.
It seems there have been other people experiencing a similar problem in this forum but without a solution so far (see e.g. https://e2e.ti.com/support/data_converters/precision_data_converters/f/73/t/351795

  • Hello Alex,

    Thanks for your question and the very detailed description.

    I'll have more time to look into this tomorrow and give you a more complete response. In the meantime, have you tried probing the output of the BIAS amplifier (BIASOUT) to confirm your measurements with an oscilloscope?

    Also, you are correct that the value of the BIASENS resistors is 220k each, as shown in the datasheet figures. I'll make a note to correct this in the next datasheet revision.

    Best Regards,
  • Hi Ryan!

    To answer this briefly: Yes i did, with both multimeter and oscilloscope. BiasOut shows the offset externally as well.

    Looking forward to hear your results!

    Best
    alex

  • Hi Alex,

    I conducted the same measurements on the bench using our ADS1299EEG-FE EVM and bipolar +/-2.5V supplies. The results for Channel 1 look almost identical as yours, but for Channel 2, the offset I measured was considerably smaller. I experimented with enabling/disabling BIASP1 and, whenever BIASP1 was enabled, the BIASOUT common-mode voltage shifted from ~5mV to ~430mV.

    I did find that, whenever BIASP2 was enabled, the BIASOUT would rail to either the positive or negative supply (depending on whether I was using unipolar or bipolar configuration). I would confirm that the BIAS_SENSP/N registers read back as expected.

    Can you please share whatever additional circuitry you may have connected to BIASOUT or BIASIN?

    Channel 1 had an offset of -514uV and an amplitude of 7.49mVpp.

    Channel 2 had an offset of 431mV and an amplitude of 6.97mVpp.

    Best Regards,

  • Hi Ryan,

    interesting. And problematic (i guess you sensed the BIAS signal also with G=1)? 
    Currently, that leads to the fact that I do not really know how to properly use the BIAS settings, if I do not want to introduce this offset to the body and by that to the other channels as well...

    Regarding your question: There is no other additional circuitry for my BIAS electrode other than that I posted in the schematics in the first thread.

    I hope we find a strategy how to deal with this!
    Best

    Alex

  • Hi Alex,

    I agree that it's problematic. And yes, everything was done with the PGA = 1. Let me me continue to look at this with a designer and I'll give you an update as soon as I can.

    Best Regards,

  • Hi Alex,

    It turns out that the internal test signal does not have the same common-mode voltage as the BIAS amplifier circuit. The difference in this common-mode voltage and the gain of the closed-loop BIAS amplifier are the cause of the large offsets you see when measuring BIASOUT.

    Internally, the test signal is generated with a mid-reference common-mode voltage. For the 4.5-V internal reference, the test signal will have a 2.25-V common-mode with respect to AVSS (the amplitude remains as described in the datasheet). Meanwhile, using your supplies, the BIASREF will be closer to 2.625V with respect to AVSS. The DC gain of your circuit with one BIAS_SENS input selected is 1M/220k = 4.545. So, 4.545*(2.625-2.25) = 1.7V. You can see this in the attached TINA-TI spice simulation.

    To reduce this DC offset, you would need to reduce the value of Rf. Fortunately, in the real application, there should not be a ~300mV difference in common-mode between the patient and the bias amplifier output.

    BIASOUT_Test Signal.TSC

    Best Regards,

  • Thanks Ryan, that totally makes sense.