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ADS1675: ADS1675 - 32Mhz Clock

Brian Cavanagh97
Prodigy 190 points

Part Number: ADS1675

Hi All,

Reading the datasheet for the ADS1675 I read a rise/fall time of 1ns.  I can't locate an oscillator that can handle that rise/fall time.  Can someone make a suggestion?

On the reference design there's a clk signal coming into the ADS1675 from an FPGA via an OR-Gate.  However, that OR-Gate doesn't handle the rise/fall time either.

Can someone assist me with this?

Thanks,

Brian

  • 0
    TI__Guru 69366 points
    Hi Brian,

    Thanks for your question. I'm looking into this for you now and will provide an explanation as soon as I have one.

    I'm not immediately sure why the "1ns rise time" was mentioned in the text, but it is not a required specification that you must meet. Given that it's included in the device overview section, this should be interpreted as more of a guideline to achieve optimal performance.

    You make a good point that the OR-gate on the EVM does not support this recommendation either - I don't have a good explanation as to why that was chosen for that design.

    Best Regards,
  • 0 in reply to Ryan Andrews
    TI__Guru 69366 points
    Brian - it turns out that the recommended 1ns rise/fall time comes from the duty cycle requirement for the master clock. In order to meet the 47% minimum duty cycle with the maximum clock frequency (32MHz), the rise/fall time must be kept to <1ns. For slower clock frequencies, a longer rise/fall time can be tolerated.

    Without meeting this spec, the device will still work. As I mentioned before, the more precise your clock is, the better performance you will get out of the device, especially in this case where the master clock directly controls the sampling timing in the modulator. Therefore, it is critical to keep clock edges sharp and jitter to a minimum.

    Best Regards,