ADS1292: A problem with the output data of ADS1292

Chris_Wang

Part Number: ADS1292

Hi guys:

I met a problem when I tried to read the 72 bits data of ADS1292 through MCU . The trouble is whatever I try to change the register parameters of CH1SET , the output data is always FF C0 0 0 1 80 0 0 FF . It looks like the channel 1 has been closed and the data is dislocated. When I checked the circuit, I found that IN3N and IN3P were connected to AGND instead of AVDD. The following parameters are my configuration.

ADS_REG(WREG|RESP1,0X02);

Hope you guys can help me to solve this problem.Thanks!

Regards,

Chris

over 8 years ago

0 Ryan Andrews over 8 years ago

TI__Guru 66706 points

Hello Chris,

What is the applied input voltage to the Channel 1 inputs? Are you able to read the register settings to confirm they are the proper value?

Best Regards,

0 Chris_Wang over 8 years ago in reply to Ryan Andrews

Prodigy 180 points

Hi Ryan,

Thanks for your help!

I found a problem of the output wave of the DRDY signal. There are two square wave in one read out cycle,just like this.

Regards,

Chris

0 Ryan Andrews over 8 years ago in reply to Chris_Wang

TI__Guru 66706 points

Hello Chris - are you seeing a normal /DRDY pattern after the device powers up? /DRDY should pulse at the default data rate. The first rising edge of SCLK forces /DRDY to clear high. If you do not read data, then /DRDY will idle low and return high a few tCLK periods before the next sample is ready.

Can you please share a capture of SCLK, /DRDY, /CS, and DOUT?

Regards,

0 Chris_Wang over 8 years ago in reply to Ryan Andrews

Prodigy 180 points

Hi Ryan,

Sorry for reply you so late.

It's looks like i have chosen a wrong edge of DRDY to read data, i use the MCU external interrupt to catch the raising edge of DRDY.

Regards,

Chris

0 Ryan Andrews over 8 years ago in reply to Chris_Wang

TI__Guru 66706 points

Hi Chris,

Did you solve your problem then? The falling edge of /DRDY is the correct edge for the MCU to use as an external interrupt.

However, I'm wondering why /DRDY is transitioning from low to high before /CS is low?

Best Regards,

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ADS1292: A problem with the output data of ADS1292