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ADS131A04: Bandwidth limitation when daisy chaining multiple ADCs

Jonathan Li
Prodigy 20 points
Part Number: ADS131A04
Other Parts Discussed in Thread: ADS131A02

The key question is - are there any limitations in bandwidth if we are daisy chaining 3 ADS131 chips together and running it at max 128ksps (in Synchronous Master Interface Mode, or any other modes)?  If so, what are the recommended solutions around this.

We're planning to daisy chain 2 ADS131A04 and 1 ADS131A02 together to string together a total of 10 channels.  Looking at the SPI bus timing requirements and the amount of data being sampled, we are concerned with the bandwidth limitations.  
Based on our calculations - 
Min SCLK Period = 2x 56ns = 102ns (Synchronous Master Interface Mode)
Max SCLK = 15.625 MHz
Max Data Rate = 1.95MB/s
 
Max Frequency 128KHz
Required Bandwidth = ((16 bit depth x 4 channels)+16 Overhead bits)*2 chips+((16 bit depth *x 2 channels) + 16 Overhead bits) * 128KHz = 3.25MB/s
 
Required Bandwidth > Max Data Rate
 
Based on our calculations, there is a bandwidth limitation. We also think the time between nDRDY to the next nDRDY does not provide sufficient time to transmit data from the 3 ADS131 chips.

 

 

  • 0
    TI__Guru**** 181111 points
    Hi Jonathan,

    Welcome to the e2e forum! You are correct in that you will need to account for all channel data and the overhead of the STATUS bytes when dealing with data retrieval of the ADS131A04 and ADS131A02. At the 128kSPS data rate, you would need to access all data channels in ~ 7.8 uS (the time between DRDY outputs) to sustain the system at this speed. Does your processor have more that one SPI peripheral? Have you considered using the devices in parallel rather than chain mode?