• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 3 answers
  • Subscribers 46 subscribers
  • Views 2793 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1299-4: Recalling the ways to get a clean signal

Kamen Ivanov
Intellectual 690 points
Part Number: ADS1299-4
Other Parts Discussed in Thread: ADS1299

Hello,

I am working on a custom board with ADS1299-4. The board seems to be in a good shape, I succeed to collect an ECG signal, I am yet to collect EEG signal, though. However, I tried the device in several locations - in home environment the ECG data appeared right away, without any difficulties. I believe this is a proof that the device itself does not exhibit significant problems (e.g. disturbances caused by the power-supply converters on the board). In office, however, there were disturbances and it was impossible to see a signal even once. I am yet to investigate the nature of those disturbances and check if I can see some signal after filtering. I am willing, however, to be able to get useful signal in such a noisy environment. Therefore, I am trying to figure out what measures to take  to suppressing the disturbance components:

- when all channels are disabled, BIASOUT voltage is about 0.5Avdd. When a channel is enabled, however, BIASOUT voltage tries to reach AVdd. I believe, during normal operation BIASOUT voltage should not diverge much from 0.5Avdd, but having it approaching Avdd perhaps indicates that the common-mode disturbance is that large so the driver tries to compensate it but is unable... Could that be the case, is that large voltage at the BIASOUT output normal at all?

- perhaps shielding of electrode connecting wires is worth to try - however, as there is an option for active shielding in ADS1299EEG-FE, does it worth to try active shielding in the custom board? Could I expect any significant decrease of external disturbances in this case?

- I found interesting notes here https://github.com/lukaszmargielewski/EEG_BLE  . Basically, that guy claims that an RLD driver without the feedback RC group could offer a great CMRR, and also, that in therms of avoiding the 50/60Hz mains disturbance, connecting the inverting input channel pins together to get a reference electrode is a better solution rather than using SRB1. Do these claims make sense, is it worth to try that?

Kind regards

  • 0
    Intellectual 690 points

    There is some additional observation to above: I found that I am getting a good ECG signal when the BIASOUT is disconnected from the patient. When it is connected, ECG signal becomes small and almost disappears.  That implies that the useful physiological signal somehow appears as a common-mode signal to the channel input, thus the ADS1299 is trying to suppress it. That also might explain why I am not able to see EEG signal yet, and also why the problem with noise in office is so terrible - perhaps the right leg driver simply does not function as intended. Any suggestions how to investigate the problem?

    Kind regards

  • 0
    TI__Guru 66346 points

    Hello Kamen,

    Thanks for your post.

    Kamen Ivanov said:
    - when all channels are disabled, BIASOUT voltage is about 0.5Avdd. When a channel is enabled, however, BIASOUT voltage tries to reach AVdd. I believe, during normal operation BIASOUT voltage should not diverge much from 0.5Avdd, but having it approaching Avdd perhaps indicates that the common-mode disturbance is that large so the driver tries to compensate it but is unable... Could that be the case, is that large voltage at the BIASOUT output normal at all?

    What is connected to the inputs during this test? If you have lead-off detection enabled and the inputs are not connected to a signal source, then they will be pulled internally to the positive or negative supplies. Then, if those inputs are selected for the BIAS derivation, the common-mode output of the BIAS amplifier can change significantly.

    If the inputs are connected and the BIAS output is still railing, try reducing the gain of the PGA and/or the BIAS amplifier. The BIAS amplifier gain is set by the feedback resistor (Rf) and the number of PGA outputs selected. Each PGA output is connected in parallel to BIASINV through a 220-kOhm resistor, so the gain is (Rf / (220k || 220k || ... )).

    Kamen Ivanov said:
    - perhaps shielding of electrode connecting wires is worth to try - however, as there is an option for active shielding in ADS1299EEG-FE, does it worth to try active shielding in the custom board? Could I expect any significant decrease of external disturbances in this case?

    If your electrode cables are coaxial, you can try tying their shields together and driving it with some common-mode signal. Ideally, you want the common-mode signals on the shield to match the common-mode signals on the electrodes, which will reduce the capacitive coupling between the two. Essentially, this means you should drive the shields to the inverse of BIASOUT.

    Kamen Ivanov said:
    - I found interesting notes here https://github.com/lukaszmargielewski/EEG_BLE  . Basically, that guy claims that an RLD driver without the feedback RC group could offer a great CMRR, and also, that in therms of avoiding the 50/60Hz mains disturbance, connecting the inverting input channel pins together to get a reference electrode is a better solution rather than using SRB1. Do these claims make sense, is it worth to try that?

    In theory, this approach can certainly work. As you increase Rf, you increase the gain of the RLD loop and further suppress the common-mode interference. Opening the feedback loop allows you to achieve the maximum gain possible, limited only by the open-loop gain of the amplifier. However, the concern that I have is with the amplifier's stability. You will encounter parasitic impedances from patient cables, electrode connections, etc. that can make the amplifier loop unstable. By closing the feedback loop immediately around the BIAS amplifier, you can better define the closed-loop bandwidth and ensure the poles/zeros from parasitic impedances are negligible. You can still increase the gain of the loop by increasing Rf and Cf, as long as you keep the closed-loop bandwidth > 50Hz/60Hz (probably best to include at least the second harmonic as well).

    Best Regards,

  • 0 in reply to Ryan Andrews
    Intellectual 690 points

    Dear Ryan,

    Thanks for the detailed explanations. Now situation is quite clear, however I would like to clarify still the following:

    - while we want to drive the shield with the inverse of the BIASOUT signal, the shield driver implemented in the

    ADS1299EEG-FE (see image below) does not seem to invert the BIASOUT signal, is that still fine?

    - I am a bit confused of the ADS1299 datasheet in terms of PGA output resistors - it is written there that "330-k? resistors at each PGA output are in parallel for common-mode signals.", while in the figures values of resistors at the outputs of PGAs are shown as 220k - are the same resistors referred in both cases, is 220k the correct value?

    - Some clarification regarding the PGA and configuring the bias calculation is welcome:

    On Fig. 23 of the datasheet, the PGA structure is shown like this:

    while in the following figures it comes as:

    I guess the last one is correct and perhaps the one from Fig. 23 has omission in exchanging the inputs of the lower OA? If so, that also explains why we can get the common mode voltage at the output of the PGA - the common mode voltage acts in the same direction to the both non-inverting inputs, and thus at the outputs of the OAs the common mode signals sums up. Is that assumption correct?

    Kind regards

  • 0 in reply to Kamen Ivanov
    TI__Guru 66346 points

    Hello Kamen,

    1. I believe that was an oversight on the EVM design. You will want to invert the BIASOUT signal to drive the cable shielding.
    2. "330k" is a typo, the correct value is 220k for the summing junction resistors connected to the BIAS amplifier. I will make a note to update it in the next datasheet revision.
    3. Both figures are correct. The first (Figure 23) is only showing the channel input path connected to the ADC. The second figure shows how we connect the same PGA outputs and route them to the BIAS amplifier inverting input through series 220k resistors. This is illustrated more clearly in Figure 72.

    Best Regards,

  • 0 in reply to Ryan Andrews
    Intellectual 690 points
    Dear Ryan,
    thanks for the answers. Let me clarify the last question: I believe the schema form fig. 23 contains a mistake since the inverting and non-inverting inputs of the lower operational amplifier seem exchanged - in this case the lower OA seems to have a positive feedback... Thus I believe that is an omission of the datasheet and wanted to confirm that.
    Kind regards,
    Kamen
  • 0 in reply to Kamen Ivanov
    TI__Guru 66346 points

    Hello Kamen,

    You have found an error in the datasheet. :) MuxP and MuxN should connect to the amplifiers'  non-inverting inputs and the feedback paths should connect to the inverting inputs.

    I will make a note of it right away and update the figure in our next datasheet revision.

    Best Regards,