ADC128S052: SCLK Duty Cycle

Hans,

SCLK is used for accessing data from the device as well as the clock source for the conversion process. This pause between 8-bit transfers adds to the total conversion time so it is better to keep this time as minimum as possible. See ADC128S052 serial timing below.

tconvert is the conversion time = 13SCLK cycles (max).

For meeting the stated performance, DS recommends a minimum clock freq of 3.2MHz so the maximum conversion time (13SCLKs) is about 4us. Beyond this droop on the sample and hold capacitors can degrade conversion results. Note: the device can function to 0.8MHz minimum SCLK so the max conversion time is 13 x 1.25 = 16.25us.

In your case, the total conversion time is a function of the serial clock frequency and the amount of pause time between 8-bit transfers. Make sure the total conversion time is within above limits.

Thanks,

Vishy

>>>> so if I am using 2 x 3.2MHz = 6.4MHz SCLK resulting in 2µs I can have a 2µs pause in between?

Yes, limit to 2us or lesser so the total conversion time specs is 4us or lesser.

>>>>But then we violate the max duty cycle...

There are two specifications in this regard (see DS snippet below) 

I understand minimum SCLK high/low time specs is important and needed to meet DIN/DOUT setup and hold time specifications. See Section 6.7 of the DS. The SCLK duty cycle of 40-60% is there mainly as an alternate way of specify SCLK high time/low time specs.

For SCLK = 6.4MHz,  you should meet minimum tCH and tCL of 62.5ns. That ensures DIN/DOUT transfers happen without issue. 

Thanks,

Vishy