Hi, I have 6 DAC6573s, with address pins A3...A0 set to 0000 to 0101 (hardwired). My problem is that devices that share A1A0 address bits both respond to reads - it is like the control byte containing A3A2 is being ignored. When the read happens, whatever zeroes are being put on the line win.
I have checked the A3...A0 pins. All voltages are unique and correct.
Write address 4c with 10 ae 80
Write address 4c with 50 0f c0
Control byte 10 has A3A2 = 00. Control byte 50 has A3A2 = 01. For the above writes, I am writing to devices 0 and 4.
Write 4c 10, repeated start, read 4c.
Data returned is 0E 80 - it's an and of the data in devices 0 and 4.
What I'm hoping to get is a clue about what else could be wrong in the data being sent is correct, the protocol looks OK (checked with scope), and the devices have the address pins set correctly.
There is a small glitch during the write after the slave completes the write ACK. This is apparently because the slave is stopping driving and the master is regaining bus control. It's supposed to be OK because SCL is not high at this time. I don't know if it actually affects the DAC6573.
Also, LDAC is being used. My understanding is that the posedge of LDAC causes the transfer from the temp reg to the DAC reg. Could it be possible that when I write the control byte before initiating the read, the register doesn't see the control byte with the A3A2 data because the LDAC hasn't come yet?
Thanks,
Marc
