DAC5311: Clocking DAC5311, 6311, 7311, 8311, 8411

 I want to use the same design with dacs of different resolutions (DAC5311, 6311, 7311, 8311, 8411).

My question: Is it allowed to send more than the required 16 or 24 CLK with SYNC/ low? I.e. if I send always 18 data bits to these devices, will those with lower resolution work correctly?

I would like to use for all the DACs the sequence shown in solid SYNC line in Figure 80 of the DAC8411 data sheet (Valid Write Sequence), but stopping clocks and data after SYNC/ going high:

In Figure1 (Serial Write Operation) of the DAC5311 data sheet this is somehow indicated, and in 8.5.1.2 SYNC Interrupt it says: "the SYNC line is kept low for at least (!) 16 falling edges of SCLK and the DAC is updated on the 16th falling edge", but in Figure 83 there are no more clocks while SYNC is low.

So: what happens if I send more data than required to the "smaller" DACs?

Thanks for your support,

Wolfgang Ruprecht, Isitronic GmbH