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ADS127L01: SPI problem ADS127L01

Lukasz Huchel
Expert 1420 points
Part Number: ADS127L01

Hi,

I am trying to establish communication between my f28379D and ADS127L01. My DSP has maximum SPI data frame of 16 bit. I am able to use stop, start, restart commands to control the ADS127L01. I am confused with the reading process. ADS127L01 continuously provides the data out once DRDY signal goes down and SCLK signal is provided. However, I need to transmit from my DSP in order to set CS and SCLK signals. I am using the RDATA 0001 0010 command for this.

Should I send this command twice after detecting change in the DRDY signal? I use 16 bit frame so I need 2 frames for 24/32 bit data from ADC. 

I am doing it now and basically my buffer is field with the same value, as if sending RDATA twice was reading the same bytes of ADC result. I am confused and will be thankful for clues.

Lukasz

  • 0
    TI__Guru 66246 points

    Hi Lukasz,

    Sorry for missing this one.

    You only need to send RDATA one time whenever you detect /DRDY goes low. If you need to send SCLK in "bursts," that is ok in SPI Mode. I believe extra SCLKs will shift out 0s at the end of the data word, which you can ignore. For Frame-Sync Mode, you must leave SCLK running continuously and synchronize it to CLK.

    What you observed is the expected behavior - that is, when you send RDATA a second time, the output shift register in the ADS127L01 will reload the data again.

    I hope this answers your question. Again, apologies for my delay.

    Best Regards,

  • 0 in reply to Ryan Andrews
    Expert 1420 points
    Hi,

    Thank you. I did find it out finally. I initialize reading once by RDATA command and then provide just sclk for another "SPI frame" to read all values up to 24/32 bits.

    Thanks.