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ADS1115BQDGSRQ1

Other Parts Discussed in Thread: ADS1115

Dear TI Engineer,

i'm already succes to read the analog value 4 channel in an ADC ADS1115, the delay time arround 1.5 mS for 860 SPS.

but i want to use 16 channel (multiple ADS1115).

I try to scan the I2C address from multiple ADC(4 IC), each ADC has different address (VDD,GND,SCL,SDA).

i'm using atmega168 to scan the i2c device. The result address for VDD,GND, SDA already appear (detected) on my atmega. but for SCL address(&B10010110) cant detect or error communication.

Datasheet item 9.5.1.1 on page 21 said it's need special treatment. can you give me sample to read ADC withh ADDR connect to SCL.

this my sub routine I2c scanner with BASIC COMPILE (BASCOM).

$regfile = "m168pdef.dat" ' the used chip
$crystal = 16000000 ' frequency used
$baud = 115200 ' baud rate


Declare Sub I2c_scan

Dim B As Byte , Status As Bit

Do
     Call I2c_scan
     Waitms 100
Loop

End

Sub I2c_scan 'check all devices on the I2c-bus
Print "Scan start"
For B = 0 To 254 Step 2
'for all odd addresses
I2cstart 'send start
I2cwbyte B 'send address
If Err = 0 Then 'we got an ack
Print "Slave at : " ; B ; " hex : " ; Hex(b) ; " bin : " ; Bin(b)
End If
I2cstop
'free bus
Next
Print "End Scan"
End Sub

Thank You

Mansur. H

  • Hello Mansur,

    I am moving this post to the correct forum for better support.

    -Francis Houde

  • Mansur,


    The requirement for using the ADDR pin connected to SCL is to hold SDA low for at least 100ns after the SCLK line goes low. This will differentiate the ADDR detecting SDA and SCL.

    To check this on your system, I would use an oscilloscope or a logic analyzer to measure SDA and SCL and make sure that there is a separation of 100ns between the two lines.

    If you are looking for help programming this, I'm not sure if we can help. I'm don't know how the Atmega168 I2C protocol is implemented, and if there is flexibility enough in the SDA and SCL timing. Also, I don't know if there's a way to add some delay (perhaps with higher resistance pull ups or with more capacitance).

    Note that without the SDA/SCL separation, you may have two devices detected at the same address, which may give I2C bus contention.


    Joseph Wu
  • Joseph Wu,
    thanks for your answer, my second question. for addressing to SCL, whe the sequent to read this address, after read ADDR connect to SDA or after ADDR connect to GND?
    OK i will try separate i2c reading for single SCL ADDR for testing the i2c communication.
  • Mansur,


    I'm not sure I completely understand your question, but let me try and explain how the ADDR pin works.

    The ADDR pin is sensed with each I2C transaction. There is a state machine that is initiated with the START condition on the I2C bus. While the I2C address is being written to the bus by the master, the device will detect if the ADDR attached to GND, VDD, SDA, or SCL. Once the address byte write is completed, the state machine completes and determines which pin ADDR connected to. If the address written is the same as the address decoded by the state machine, then the device responds with an ACK. If the address does not match, then the device does not respond.

    I hope that helps answer your question, let me know if you need to follow up.


    Joseph Wu