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ADS1258

Other Parts Discussed in Thread: ADS1258

I have a couple of questions about this converter:

1) If I read the datasheet correctly one could start the converter in autoscan mode with all 16 channels selected and never stop it.
   And then read the channel data as needed with Channel Data Read Commands. Is this correct?
2) Very little is said about the Channel Data Read Command.
   For Register Read Command automatic incrementing of register address is discussed.
   But there is no mention of a similar index for Channel Data Read Command. I assume that the device behaves this way.
   Is this correct? If so, does Channel Data Read Direct also work with a auto-increment mechanism?
3) I seem to be having a problem with the Register Write Command. I follow each of these commands with a Register Read Command but
   I do not always get the value that I just wrote. The device behavior also seems to indicate that the write did not occur properly.
4) In Autoscan mode it appears that DRDY asserts at the end of each conversion cycle - if one channel is selected after it is converted
   (approx. 43.75 us) - if 16 channels are selected after it has converted all sixteen channels (approx. 700 us, 1.4 ms if CHOP is enabled).
   Is this correct?

Charlie

  • Hi Charlie, 

    Answers to your questions are below in blue

     

    1) If I read the datasheet correctly one could start the converter in autoscan mode with all 16 channels selected and never stop it. 
       And then read the channel data as needed with Channel Data Read Commands. Is this correct?

    Yes, you can use that method. Note that the ADS1258 architecture is a single A/D converter with a built in mux. For that reason, the ADC has a single output register that is updated with the conversion result every time that /DRDY pulses. For that reason, you need to monitor the /DRDY pulse and use the channel data read command every time the /DRDY pulses. You also have the option to run the ADC in channel data read direct which in includes no command. Therefore, once /DRDY goes low, you begin sending SCLKs and the ADC will output the data. See the data sheet for more information on operating modes


    2) Very little is said about the Channel Data Read Command. 
       For Register Read Command automatic incrementing of register address is discussed. 
       But there is no mention of a similar index for Channel Data Read Command. I assume that the device behaves this way.
       Is this correct? If so, does Channel Data Read Direct also work with a auto-increment mechanism?

    This specific ADC has a single output register that is updated with the conversion result from every channel. Table 11 on page 33 of the data sheet breaks down the channel pointer index showing the sequence that the output register is updated in. You will need to make sure that you read out the converted data before /DRDY pulses again indicating that the output reg has been updated. If you do not monitor /DRDY, you may miss a conversion result. 


    3) I seem to be having a problem with the Register Write Command. I follow each of these commands with a Register Read Command but
       I do not always get the value that I just wrote. The device behavior also seems to indicate that the write did not occur properly.

    Do you have an issue writing to set up the registers and then trying to read them back? Make sure you review the command byte configuration on page 34 of the data sheet (enable or disable the MUL bit, etc.). Also, make sure you are using the correct edge of SCLK as the critical edge. The rising edge of SCLK is the critical edge so make sure that the input data is changing on the falling edge of SCLK so it is stable at the rising edge of SCLK.  Do you always have problems writing to registers, or just some of the time?


    4) In Autoscan mode it appears that DRDY asserts at the end of each conversion cycle - if one channel is selected after it is converted 
       (approx. 43.75 us) - if 16 channels are selected after it has converted all sixteen channels (approx. 700 us, 1.4 ms if CHOP is enabled).
       Is this correct?

    You are correct. The ADS1258 is a single converter with a mux in front of it. So the 23.7kSPS data rate is the speed for a single conversion of a single channel. So to read back all 16 channels single ended, it would take 700uS (1.4 ms with CHOP enabled). 

     

    Regards,

    Tony Calabria

     

  • Do you have an issue writing to set up the registers and then trying to read them back? Make sure you review the command byte configuration on page 34 of the data sheet (enable or disable the MUL bit, etc.). Also, make sure you are using the correct edge of SCLK as the critical edge. The rising edge of SCLK is the critical edge so make sure that the input data is changing on the falling edge of SCLK so it is stable at the rising edge of SCLK.  Do you always have problems writing to registers, or just some of the time?

    We have write failures only sometimes. Command byte structure is fine - MUL is always off for register access - only ever access one at a time. Since we are using a uP running at 24 MHz (41.6 ns cycles) to manipulate all ADC control and data signals I think that it is impossible to violate the DIN setup and hold times of 20ns and 5ns respectively. But we do have NOP padding for good measure.

    Regards, Charlie

  • Hi Charlie, 

    Looks like your SCLK speed may be too fast for this converter. The speed of your master clock (fclk) sets the limit for the SCLK speed. If you look at page 6 of the data sheet, we spec the SCLK period as min 2 tclk (master clock) periods. The fastest the master clock can run is 16 MHz (pg 3 of data sheet), and if it is run at that speed, the SCLK can be a max of 8 MHz. You may not be violating the setup and hold times but you are violating the max SCLK frequency if you are using a 24MHz signal. Try slowing down your SCLK, this should fix your issue. 

    Regards,

    Tony 

  • Tony,

    Thank you for your response. I apologize for taking so long to get back to this - I was busy off working on a diferent tangent for a while.

    Thank you for the suggestion. My SLCK is OK w.r.t. speed though - I am clocking it far below an 8 MHz rate. But I think you are very close to the problem. It seems that the PLL is running unstable. We are now investigating the clock.

    I have another unrelated question. It is not clear how to use the internal OFFSET value. I assume that the sign indicates the direction of error - if positive, I need to subtract the value in order to compensate for it - if negative, I need to add the value in order to compensate for it. Is this correct?

  • Hi Charlie, 

    You are correct, depending on whether the offset reading is positive or negative, you will need to add or subtract the error. Positive relates to a positive offset error which needs to be subtracted and negative is a negative offset error which needs to be added. You can do this by adding subtracting the ''codes'' or convert everything to volts and add/subtract the volts.

    Regards,

    Tony Calabria 

  • One more thing - 

    If you are concerned with offset error, I would consider using the CHOP feature that is integrated in the ADS1258. The CHOP feature takes two measurements, one with the inputs one way, and one with the inputs switched, and averages the two. This greatly reduces any offset error in the device. You can read more about CHOP in the ADS1258 data sheet. 

    Regards,

    Tony 

  • Tony,

    Do you mean to say that if I enable chop mode the internal OFFSET value is not useful? I thought that chop mode took care of offsets up to the point of ADCIN and OFFSET gave you the value of any offset in the ADC. Was my understanding wrong?

     

    Charlie

  • Hi Charlie, 

    The CHOP feature will eliminate a lot of the offset that is associated with the ADC inputs but will not completely eliminate it. You can see on page 3 of the data sheet that we spec the offset voltage with CHOP enabled and disabled. Enabling CHOP greatly reduces the offset, from 20 uV typical to 1uV typical. There is still an offset voltage component coming from internal circuitry that you will be able to read back from the OFFSET value. 

    Regards,

    Tony Calabria