DAC8775EVM: dac8775

siddhant kumar

Part Number: DAC8775EVM
Other Parts Discussed in Thread: DAC8775

Hello experts!

I need VHDL code of SPI to check the output of the DAC8775EVM, I am unable to get the output with my spi. Kindly share code with me, it would be very helpful for me.

Thanks.

over 8 years ago

0 Matthew Sauceda over 8 years ago

TI__Genius 11750 points

Howdy Siddhant and welcome to the e2e forums!

Have you been able to verify the SPI transaction by reviewing an oscilloscope capture? The SPI communication command consists of a write address byte and a data word for a total of 24 bits (when CRC is disable). Additionally, you will need to verify the timing requirements are met, which are shown in the "Timing Requirements: Write and Readback Mode" section of the datasheet -- page 13.

Unfortunately we don't have any examples of VHDL code for the SPI transaction, but if you are opting on using a microcontroller platform for communication, such as the MSP430 or similiar, I would recommend that you visit the TI microcontroller forum. They may be able to provide you with assistance in writing the SPI routine using Code Composer or a similar IDE.

Best Regards,
Matt

0 siddhant kumar over 8 years ago in reply to Matthew Sauceda

Prodigy 50 points

Hi Matthew,

I am doing great, thanks, I hope you are well too.

Yes I captured the SPI transaction using Oscilloscope both i.e first with that DAC8775EVM software, and second that of My FPGA output, Somehow both waveform looked same I mean shape wise. Still I am not getting output. Only difference is that my FPGA output is continuous meaning those writing registers ( Buck boost select >> config Buck Boost >> select DAC Register >> Config DAC register >>Data DAC register ) are being repeated, therefore my question is :

1) How to stop this repetition ( I attached the VHDL file herewith this post ).

2) Additionally what changes I need to make in this code in order to get output from DAC8775, I am not getting any output at all, I have not observed output so far.

Please share some guidelines and kindly provide me some helpful resources.

Note: I am using ALTERA Board Cyclone II, it generates 50mhz system clock ,and my SCLK frequency is 20 mhz.

Thanks and Regards

Fullscreen Top_Dac.txt Download

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:03:00 08/19/2017 
-- Design Name: 
-- Module Name:    Top_Dac - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Top_Dac is
    Port (	CLK_50MHz 		: in  STD_LOGIC;  -- system clock
				-------------SPI singal declarations-------------
				SPI_SEL			: out std_logic;
				RESET				: out std_logic;
				SPI_SCK			: out std_logic;
				SPI_DIN			: in 	std_logic;
				SPI_DOUT			: out std_logic;
				SPI_LDAC			: out std_logic
--				-------------UART Interface----------------------
--				FPGA_UART_TX	: out std_logic;
--				FPGA_UART_RX	: in 	std_logic;
--				-------------LED Signal Declarations-------------
--				LED				: out std_logic_vector(7 downto 0)				
		);
end Top_Dac;

architecture Behavioral of Top_Dac is


component clk_40
	PORT
	(
		areset		: IN STD_LOGIC  := '0';
		inclk0		: IN STD_LOGIC  := '0';
		c0				: OUT STD_LOGIC ;
		locked		: OUT STD_LOGIC 
	);
end component;


	
	COMPONENT Reg_Data_Set
	PORT(
				clk		: IN std_logic;          
				rst 		: OUT std_logic;
				spi_en	: OUT std_logic;
				spi_data : OUT std_logic_vector(15 downto 0);
				spi_addr : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;
	
	COMPONENT DAC8775_SPI
		PORT	(
				clk			:	 IN STD_LOGIC;
				rst			:	 IN STD_LOGIC;
				en				:	 IN STD_LOGIC;
				spi_din		:	 IN STD_LOGIC;
				spi_clk		:	 OUT STD_LOGIC;
				spi_en		:	 OUT STD_LOGIC;
				ldac			: 	 OUT STD_LOGIC;
				spi_dout		:	 OUT STD_LOGIC;
				spi_addr		:	 IN STD_LOGIC_VECTOR(7 DOWNTO 0);
				spi_data		:	 IN STD_LOGIC_VECTOR(15 DOWNTO 0);
				spi_rd_data	:	 OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
				data_rdy		:	 OUT STD_LOGIC
				);
	END COMPONENT;

	
	--signal Clock_40MHz_wire : std_logic;
	--signal locked_wire		: std_logic;
	signal Reset_Reg_data	: std_logic;
	signal En_Reg_data		: std_logic;
	signal Data_Reg_data		: std_logic_vector(15 downto 0);
	signal address_Reg_data	: std_logic_vector(7 downto 0);	
	signal spi_rd_data		: std_logic_vector(15 downto 0);
	signal spi_data_rdy		: std_logic;
	signal spi_din_top		: std_logic;
	signal spi_clk_top		: std_logic;
	signal spi_en_top			: std_logic;
	signal spi_dout_top		: std_logic;
	signal locked_wire		: std_logic;
		signal clock_40		: std_logic;
Begin
clk_40_inst : clk_40 PORT MAP (
		areset	 => '0',
		inclk0	 => CLK_50MHz,
		c0	 => clock_40,
		locked	 => locked_wire
	);

	Inst_Reg_Data_Set: Reg_Data_Set PORT MAP(
										clk 		=> clock_40 ,
										rst 		=> Reset_Reg_data,
										spi_en 	=> En_Reg_data ,
										spi_data => Data_Reg_data,
										spi_addr => address_Reg_data
	);
								
	U2 : DAC8775_SPI port map (
										clk			=>	clock_40,										
										rst			=> Reset_Reg_data,
										en				=> En_Reg_data,
										spi_din		=> SPI_DIN,				--spi_din_top,
										spi_clk		=> SPI_SCK,				--spi_clk_top,
										spi_en		=> SPI_SEL,				--spi_en_top,
										ldac			=> SPI_LDAC,			--LDAC signal,
										spi_dout		=> SPI_DOUT,			--spi_dout_top,
										spi_addr		=> address_Reg_data,
										spi_data		=> Data_Reg_data,
										spi_rd_data	=> open,
										data_rdy		=> open
									 );
--
									RESET <= Reset_Reg_data	;			 
--SPI_DIN <= spi_dout_top;
--SPI_SCK <= spi_clk_top;
--SPI_SEL <= spi_en_top;
--SPI_DOUT<= spi_din_top;								
											
											
end Behavioral;

Fullscreen Reg_Data_Set.txt Download

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:03:34 08/19/2017 
-- Design Name: 
-- Module Name:    Reg_Data_Set - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

	       
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Reg_Data_Set is

Port (clk		: in std_logic;
		rst 		: out std_logic;
		spi_en 	: out std_logic;
		spi_data : out std_logic_vector (15 downto 0);
		spi_addr : out std_logic_vector (7 downto 0)
		--wait_st	: out		STD_LOGIC:='0'
	  );
end Reg_Data_Set;

architecture Behavioral of Reg_Data_Set is

signal count : std_logic_vector (15 downto 0):= (others =>'0');

begin

process (clk, count)

begin
	if (rising_edge(clk)) then

		count <= count + 1;
		if (count <= 5 and count >= 0) then
			rst <='0';
			spi_en <='0';
--			spi_addr <= x"01";
--			spi_data <= x"0000";
		else
			rst <= '1';
		end if;
		---------------------- Write Operation Register ----------------------
		if (count >= 110  and count <= 140) then      
			spi_en <='1';			
			spi_addr <= x"06";           		 				--- Select Buck-Boost --
			spi_data <= x"000F";

		elsif (count >=510 and count <= 540  ) then
			spi_en <='1';
			spi_addr <= x"07";
			spi_data <= x"021D";  								-- Config Buck-Boost ---
		elsif (count >= 880 and count <= 910) then
			spi_en <='1';
			spi_addr <= x"03";
			spi_data <= x"01F1";        			  		 	-- Select DAC Register ---
		elsif (count >= 1250 and count <= 1280) then
			spi_en <='1';
			spi_addr <= x"04";
			spi_data <= x"1000";           				 	--- Config DAC Register ---
		elsif (count >= 1620 and count <=1650) then
			spi_en <='1';
			spi_addr <= x"05";
			spi_data <= x"FFFF";										---DAC Data Register ---
		elsif(count>=1990 and count <=2020) then
		spi_en <='1';
		spi_addr <= x"00";
		spi_data <= x"0000";	
	

--			
	------------------------------------------------------------------------------------
--		elsif (count >= 510 and count <= 540) then
--			spi_en <='1';
--			spi_addr <= x"0037";
--			spi_data <= x"00";
--		elsif (count >= 610 and count <= 640) then
--			spi_en <='1';
--			spi_addr <= x"0037";
--			spi_data <= x"00";
--		elsif (count >= 710 and count <= 740) then
--			spi_en <='1';
--			spi_addr <= x"0037"; 
--			spi_data <= x"00";
--		elsif (count >= 810 and count <= 840) then
--			spi_en <='1';
--			spi_addr <= x"0037";
--			spi_data <= x"00";
--		elsif (count >= 910 and count <= 940) then
--			spi_en <='1';
--			spi_addr <= x"8014";
--			spi_data <= x"00";
--		elsif (count >= 1010 and count <= 1040) then
--			spi_en <='1';
--			spi_addr <= x"8014";
--			spi_data <= x"00";
--		elsif (count >= 1110 and count <= 1140) then
--			spi_en <='1';
--			spi_addr <= x"8293";
--			spi_data <= x"80";
--		elsif (count >= 1210 and count <= 1240) then
--			spi_en <='1';
--			spi_addr <= x"8294";
--			spi_data <= x"00";
--		elsif (count >= 1310 and count <= 1340) then
--			spi_en <='1';
--			spi_addr <= x"82AB";
--			spi_data <= x"07";
--		elsif (count >= 1410 and count <= 1440) then
--			spi_en <='1';
--			spi_addr <= x"82AC";
--			spi_data <= x"FF";
--		elsif (count >= 1510 and count <= 1540) then
--			spi_en <='1';
--			spi_addr <= x"8009";
--			spi_data <= x"17";
--		elsif (count >= 1610 and count <= 1640) then
--			spi_en <='1';
--			spi_addr <= x"FFFF";
--			spi_data <= x"FF";
--		elsif (count >= 70 and count <= 110) then
--			spi_en <='1';
--			spi_addr <= x" ";
--			spi_data <= x" ";
--		elsif (count >= 70 and count <= 110) then
--			spi_en <='1';
--			spi_addr <= x" ";
--			spi_data <= x" ";
--		elsif (count >= 70 and count <= 110) then
--			spi_en <='1';
--			spi_addr <= x" ";
--			spi_data <= x" ";
--		elsif (count >= 70 and count <= 110) then
--			spi_en <='1';
--			spi_addr <= x" ";
--			spi_data <= x" ";
--		elsif (count >= 70 and count <= 110) then
--			spi_en <='1';
--			spi_addr <= x" ";
--			spi_data <= x" ";
--		elsif (count >= 70 and count <= 110) then
--			spi_en <='1';
--			spi_addr <= x" ";
--			spi_data <= x" ";
		else
			spi_en <='0';
		end if;
	end if;
end process;

end Behavioral;

Fullscreen DAC8775_SPI.txt Download

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:04:18 08/19/2017 
-- Design Name: 
-- Module Name:    DAC8775_SPI - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:03:30 02/06/2014 
-- Design Name: 
-- Module Name:    AD9361_SPI - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DAC8775_SPI is
Port(	clk,rst,en	: in std_logic;              	-- System Clock
		spi_din 		: in std_logic;
		spi_clk 		: out std_logic;					-- SPI Clock
		spi_en 		: out std_logic;
		ldac			: out std_logic; 					--LDAC signal
		spi_dout 	: out std_logic;
		spi_addr 	: in std_logic_vector (7 downto 0);
		spi_data 	: in std_logic_vector (15 downto 0);
		spi_rd_data : out std_logic_vector (15 downto 0);
		data_rdy 	: out std_logic
	 );
end DAC8775_SPI;

architecture Behavioral of DAC8775_SPI is

type states is (idle, start_spi,write_high, write_low, read_high, read_low, rd_data_high, rd_data_low,write_low_end,write_high_end,rd_data_low_end);
signal c_s,n_s : states;

signal count 			: integer range 0 to 24;
signal rd_count 		: integer range 0 to 24;
signal addr_temp 		: std_logic_vector (7 downto 0);
signal rd_data_temp 	: std_logic_vector (15 downto 0);
signal wr_data_temp 	: std_logic_vector (15 downto 0);
signal send_temp 		: std_logic_vector (23 downto 0);

--attribute KEEP : string;
--attribute KEEP of spi_addr		: signal is "TRUE";


begin
process(clk,rst)
begin
	If rising_edge (clk) then
		if (rst='0') then
			spi_clk 			<='0';
			spi_en 			<='1';
			ldac				<='0';
			spi_dout 		<='0';
			spi_rd_data 	<= (others=>'0');
			data_rdy 		<= '0';
			count 			<= 23;
			rd_count 		<= 0;
			rd_data_temp 	<= (others=>'0');
			addr_temp 		<= spi_addr;
			send_temp 		<= addr_temp & wr_data_temp;
			wr_data_temp 	<= spi_data;
			data_rdy 		<='0';
		else
			c_s <= n_s;
			case n_s is
				when idle =>
					spi_clk 			<='0';
					spi_en 			<='1';
					ldac				<='0';
					spi_dout 		<='0';
					addr_temp 		<= spi_addr;
					wr_data_temp 	<= spi_data;
					spi_rd_data 	<= rd_data_temp;
					send_temp 		<= addr_temp & wr_data_temp;
					count 			<= 23;
					rd_count 		<= 15;
					data_rdy 		<= '1';
					
				when start_spi =>
					send_temp 	<= addr_temp & wr_data_temp;
					count 		<= 23;
					rd_count 	<= 15;
					spi_en 		<='0';
					ldac			<='1';

				when write_high =>
					spi_clk 	<='1';
					spi_dout <= send_temp(count);
					
				when write_low =>
					spi_clk 	<='0';
					count 	<= count -1;
					
				when write_high_end =>
					spi_clk 	<= '1';
					spi_dout <= send_temp(count);

				when write_low_end =>
					spi_clk <='0';
					

				when read_high =>
					spi_clk 	<='1';
					spi_dout <= send_temp(count);
					data_rdy <='0';
					
					
				when read_low =>
					spi_clk 	<='0';
					spi_dout <= send_temp(count);
					count 	<= count - 1;
					data_rdy <='0';

				when rd_data_high=>
					spi_clk 	<='1';
					spi_dout <= '0';
					rd_data_temp(rd_count)<= spi_din;
					data_rdy <='0';
					
				when rd_data_low =>
					spi_clk 	<='0';
					rd_count <= rd_count-1;
					data_rdy <='0';
					
				when rd_data_low_end =>
					spi_clk 	<='0';
					data_rdy <='0';

				when others =>
					spi_clk 			<='0';
					spi_en 			<='1';
					ldac				<='0';
					spi_dout 		<='0';
					spi_rd_data 	<= (others=>'0');
					data_rdy 		<= '0';
					count 			<= 23;
					rd_count 		<= 0;
					rd_data_temp 	<= (others=>'0');
					addr_temp 		<= (others =>'0');
					wr_data_temp 	<= (others =>'0');
					send_temp 		<= (others =>'0');
					data_rdy 		<='0';
			
			end case;
		end if;
	End If;
end process;
	
-----------STATE MACHINE OPERATION-----------

process (c_s,en,addr_temp,count,rd_count )
begin
	n_s <= c_s;
	
	case c_s is
		when idle =>
			if (en='1') then
				n_s <= start_spi;
			else
				n_S <= idle;
			end if;

		when start_spi => 
			if (addr_temp(7)='0') then
				n_s <= write_high;
			else
				n_s <= read_high;
			end if;

		when write_high =>
				n_s <= write_low;
			
		when write_low =>
			if (count =0) then
				n_s <= write_high_end;
			else
				n_s <= write_high;
			end if;
			
		when write_high_end =>
			n_s <=write_low_end;
			
		when write_low_end =>
			n_s <= idle;

		when read_high =>
				n_s <= read_low;
			
		when read_low =>
			if (count <= 15) then
				n_s <= rd_data_high;
			else
				n_s <= read_high;
			end if;

		when rd_data_high =>
			if (rd_count <= 0) then
				n_s <= rd_data_low_end;
			else
				n_S <= rd_data_low;
			end if;

		when rd_data_low =>
			n_s <= rd_data_high;
			
		when rd_data_low_end =>
			n_s <= idle;
			
		when others =>
			n_s <= idle;

		end case;
end process;	

end Behavioral;

0 Matthew Sauceda over 7 years ago in reply to siddhant kumar

TI__Genius 11750 points

Howdy Siddhant,

It looks like this post was created twice, and I have referenced the latest reply at the following link:

e2e.ti.com/.../2309215

Best Regards,
Matt

Data converters

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DAC8775EVM: dac8775