• State TI Thinks Resolved
  • Locked Locked
  • Replies 12 replies
  • Answers 2 answers
  • Subscribers 49 subscribers
  • Views 3985 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC32RF45EVM: Question on JESD initialization

Shawn Bish
Prodigy 170 points

Part Number: ADC32RF45EVM
Other Parts Discussed in Thread: ADC32RF45

Hardware setup:

  • ADC32RF45 EVM is connected to FMC connector on Hitech Global HTG 830 board
  • ADC32RF45 placed in Bypass LMFS82820 Mode
  • 2nd Nyquist Zone operation
  • EVM Configuration Files:  “LMK_ ADC32RF45_LMF_82820_ExtClock.cfg” and “ADC32RF4x_12bit_LMFS_82820.cfg”
  • EVM GUI is used to configure ADC and LMK settings
  • Xilinx JESD204 core is used in FPGA

I am unable to successfully connect over JESD until checking and then un-checking the "Invert SYNC Polarity" check-box on the EVM GUI.  I do see the SYNC signal inside the FPGA assert when toggle the check box on the GUI.  The SYNC signal is an output from the FPGA and an input to the ADC, so this does not make sense to me.  Any help would be greatly appreciated.  

  • 0
    TI__Mastermind 29220 points

    Hi,

    yes, you will have to change the configuration file that you are using for the ADC programming to not invert the SYNC polarity.    Preproduction silicon had the polarity of the SYNC input inverted and so the ini file that we used for HSDCPro and the TSW14J56 would have a line entry for inverting the SYNC.   Then when final silicon was available with SYNC not inverted, we already had many copies of the HSDCPro out there with the inverted SYNC so I just inverted it again in the configuration for the ADC.    That works fine until you wish to use the configuration file for the ADC with some other FPGA programming, as you are.

    The line in the config file for the ADC that inverts the SYNC is

    ADC32RFxx_ANALOG
    0x0058 0x20     // SYNC polarity inverted as the hsdcpro.ini inverts the sync

    Remove these lines, or at least the line for address 0x0058.   Or use the config file as is, and then use the GUI tab to turn off the SYNC invert as you have been doing.

    Regards,

    Richard P.

  • 0
    TI__Genius 12780 points
    Hi Shawn,

    I would check to make sure that your P/N pins of the SYNC on the FPGA are not swapped. I am including others to take a look at this issue as well.

    Regards,

    Dan
  • 0 in reply to Richard Prentice
    Prodigy 170 points
    What I have found is that just turning off "Invert SYNC Polarity" is not good enough. My JESD link doesn't get up-and-running until I toggle the box "unchecked-checked-unchecked".
  • 0 in reply to Shawn Bish
    TI__Mastermind 29220 points

    Hi,

    that makes me think that the SYNC signal from your FPGA is a static value, and you are making it look like it provides a 'pulse' to the ADC by inverting the polarity of the expected signal and then inverting it back again.   This would look like SYNC is toggling even though the actual value of the signals on the traces are not changing.  if you remove that line from the config file such that the ADC expects default SYNC polarity, then watch what your FPGA is driving for SYNC and make sure you are driving the right signal pair through the FMC connector - like driving the primary SYNC pair and not the alternate SYNC pair that is defined for the connector.

    Regards,

    Richard P.

  • 0 in reply to dBrock
    Prodigy 170 points
    I don't think this is the issue. I can invert the polarity of SYNC being driven by the FPGA. Either way I have it set, I have to "uncheck, check, uncheck" the "Invert SYNC Polarity" box to get JESD connected.
  • 0 in reply to Richard Prentice
    Prodigy 170 points
    Yes I see what you are saying. I don't know what you are referring to concerning the "alternate SYNC pair". I did, however, track my SYNC connections from the ADC32RF45 EVM to the FPGA.

    ADC Pins 35 & 36 --> EVM FMC Pins G12 & G13 --> HTG FMC Pins G12 & G13 --> FPGA Pins BE8 & BF8

    I have not probed the SYNC signal on the EVM yet. I'll do that to see if it ever toggles.
  • 0 in reply to Shawn Bish
    Prodigy 170 points
    I probed SYNC at the input to the ADC and see no transitions when the FPGA drives the signal. I do see the signal toggle, however, when the FPGA is configuring. I don't have the layout information for the carrier board and my connections look correct according the the documentation, so I decided to try to use the single ended SYNC on pin 63 of the ADC. I wired over another I/O signal from the FPGA to the test point on the EVM board and now see the signal toggling.

    When I try to enable CMOS SYNCB by writing 0x40 to registers 0x690036 and 0x1690036 using the low-level access of the EVM GUI, I can never read back the written value. I have never had this issue before when writing to other registers. Is there something else I need to do to properly enable CMOS SYNCB? Thanks, Shawn
  • 0
    Prodigy 170 points
    I spent some time trying to get single-ended SYNC working. If I just modify “ADC32RF4x_12bit_LMFS_82820.cfg” by writing 0x40 to registers 0x690036 and 0x1690036 in the JESD setup section of the script, read-back of the registers values from the ADC GUI doesn't even reflect that the script executed correctly. This is the case even without a single-ended SYNC wire attached from the FPGA to the ADC. Is there any additional setup that I need to perform to make single-ended SYNC work?
  • 0 in reply to Shawn Bish
    TI__Mastermind 29220 points

    Hi,

    I have asked the design team if there is any additional information that is needed for the programming for single ended SYNC.   For example, later in the register map is a register for setting the direction of the GPIO pin that is used for single ended SYNC, but the default direction is as input so that should not be an issue.   So I have asked if there is anything else that I need to know to use this feature.   I know that we have had applications use the single ended SYNC so it can be done. 

    Still, it sounds like your FPGA JESD IP is giving up on the attempt to establish a link after SYNC fails and thus SYNC doesn't toggle any more.   Our IP does not give up, I believe, so it may be a default setting somewhere for the FPGA IP as to how many SYNC attempts to do before giving up.   Maybe.    But have you tried removing that line in the config that set SYNC to be inverted polarity, so that the link would successfully establish the first time as it is supposed to with the differential SYNC?

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 170 points
    Richard, Thanks for forwarding that to the design team.

    Yes, I have tried configuring with inverted sync disabled to no avail.

    I also tried using the "SPI SYNC" registers to toggle SYNC internally to the FPGA, but that didn't work either. So far the "Invert SYNC Polarity" check-box is the only way I can get the link up.
  • 0 in reply to Shawn Bish
    TI__Mastermind 29220 points

    Hi,

    This is what I got back from the design team.

    There are two things we need to clarify to convert pin# 63 as CMOS SYNC:

    1. CH bit should be set to '1'.

    2. Bit 0 of register address 0x3C also has to be set to '1'. This register is not present in datasheet. We are including it in new revision of datasheet.

     

    So the necessary SPI sequence is:

    1. Access the page 0x690000

    0x4001 0x00

    0x4002 0x00

    0x4003 0x00

    0x4004 0x69

    2. Keep CH=1, and set bit 6 of reg 0x36, and bit 0 or reg 0x3C to '1'.

    0x7036 0x40 // bit <6>

    0x703C 0x01 // bit<0>

     

    (and for the record, the normal differential SYNC should work as well.  We have this EVM working with three different Xilinx development platforms and two of our capture cards with Altera devices with no issues other than getting the polarity correct.  Since you could make the differential SYNC work by manually toggling the polarity control, and you don't see the FPGA toggle the signal after first failing to initialize, I have to think there is something simple that is preventing link init and the FPGA is coded to not go back and retry.)

    Regards,

    Richard P.

  • 0 in reply to Shawn Bish
    TI__Intellectual 785 points
    Hi Shawn,

    To enable single-ended SYNC, following register writes are required:
    1. Access the page 0x690000
    0x4001 0x00
    0x4002 0x00
    0x4003 0x00
    0x4004 0x69
    2. Keep CH=1, and set bit 6 of reg 0x36, and bit 0 of reg 0x3C as HIGH.
    0x7036 0x40 // bit <6>
    0x703C 0x01 // bit<0>

    Please note Both bit<6> in address 0x036 and bit<0> in address 0x03C should be set HIGH to enable single-ended CMOS SYNC on pin# 63 of device. (The device datasheet mentions only bit<6> of address 0x036 as CMOS SYNC - this will be corrected in next revision)

    Regards,
    Sourabh