TSW14J56EVM: HSDC Pro SW Freezes when run using TSW14J56RevD & DAC38RF8xEVM (windows-7) operating System

Walter Washington

Part Number: TSW14J56EVM

Dear T.I. Forum Moderator,

Hello my name is Walter C. Washington on-site Engineer for Tyvak (Tyvak Cell: 949.300.9800) (Tyvak Email: Walter.Washington@tyvak.com)

Having similar problems to John C. posted on forum 07 June 2017:

I have installed HSDC Pro SW V4.70 onto my Win7 Pro Tower Desktop to be used in conjunction with the TSW14J56 EVM (along with a DAC83RF8xEVM connected to it).

I have followed the installation instructions, powered up the boards and can see the TSW14J56 USB device enumerate properly in the Win7 Device Manager window

(it shows "Cypress FX3 USB Streamer Example Device") and I have verified that it is plugged into the USB 3.0 port on the desktop. Also have the DAC38RF8xEMV

plugged into Tower Desktop onto another USB 3.0 port.

When I run try to follow the DAC38RF8xEVM User Guide (SLAU671A–October 2016–Revised March 2017) [see figure 7 page-9: & figure 9 page-11]

one can only get to step 8 in section 2.1.6. When I get to step 8 (click [Send] button in HSDC GUI, an error box pops up saying

"Error 1097 occurred at Call Library Function Noe in TSW1400.lvlib:14J56refD_2's complement.vi->TSW1400.lvlib:frame.vi".

Please see the attached screenshot. I have closed & re-opened the GUI's several times (along with power cycling the DAC & FPGA boards) but still get the same result.

Step Followed:

A. Invoke DAC38RF8xEVM Software GUI as administrator with the following setting shown below:

Steps taken: i) Invoke DAC RESETb Pin ii) Load Defaults iii) Configure DAC iv) PLL Auto Tune

Figure-1

B. Invoke HSDC Pro Software GUI as administrator with the following setting shown below:

ii)

iii)

iv)

vi)

NOW IMPLEMENTING SECOND ATTEMPT

vii) Prior to loading the DAC38RFx_LMF_841 setting to match “Figure-1” but after loading FPGA firmware as seen in “ii)”

note the following “Interface Type = TSW14J56REVD_FIRMWARE; Firmware Version = 0.1 displays

viii) After loading the DAC38RFx_LMF_841 setting to match “Figure-1” the setting for Interface Type is as follows: “Interface Type = ; Firmware Version = 0.1 remains

ix)

NOW IMPLEMENTING THIRD ATTEMPT

Conclusion:

Since this full tower desktop PC has 8 USB 3.0 ports and 2 USB 2.0 ports; going through all combinations will be exhaustive and timely. Please share any known

issues or possible solutions.

Thank You,

Walter C. Washington

over 7 years ago

0 Ebenezer Dwobeng over 7 years ago

TI__Genius 9695 points

Hi Walter,

-Can you check the current limit is at least 4A on the bench power supply feeding TSW14J56 EVM?

- Also make sure jumper JP10 on DAC38RF8x EVM is removed for on-chip PLL use case.

Thanks,

Eben.

0 Walter Washington over 7 years ago in reply to Ebenezer Dwobeng

Prodigy 80 points

Power supply has a current limit of 2.75A right now and both boards powered up have never gone above
2.40A. J10 has always been removed.

Actions being taken:
- Shall place DAC38RF8xEVM on separate supply with 5V 2 3A rating
- Shall place TSW14J56EVM on separate supply with 5V @ 3A rating

0 Walter Washington over 7 years ago in reply to Walter Washington

Prodigy 80 points

Now after placing the DAC38RF8xEVM & TSW14J56RevD on separate power supplies 5V @ 3A max which common ground.

One get the following error message

Current lane rate is 3.84G

JESD reference clock from device EVM

to TSW14J56RevD needs to be set at 96M

Does this mean one must manually get the a clock from the DAC38RF8xEVM

to the TSW14J56RevD board.

Clock on the EVM board which go back down the TSW are as follows CAR_SYSREF(P/N) ; FPGA_CLK1_(P/N), and FPGA_CLK2_(P/N)

Regards,

Walter C. Washington

0 jim s over 7 years ago in reply to Walter Washington

TI__Guru* 91947 points

Walter,

This is a normal status window. The DAC EVM will be sending this clock to the TSW14J56EVM assuming you loaded the LMK properly, which is what it looks like from what I can tell by your screen shots. Do you have an external 384MHz clock connected to J4? Did you click on the "PLL AUTO TUNE" button after configuring the DAC? Did you click on the "Send" button on the HSDC Pro GUI? After this, did you click on "Reset DAC JESD Core & SYSREF TRIGGER" button on the DAC GUI? If so, you should see an output at the DAC SMA's.

Regards,

Jim

0 Walter Washington over 7 years ago in reply to jim s

Prodigy 80 points

J4 has 384Mhz clock input at 6dBm. Followed all the steps you have mentioned up to Section 2.1.6 step 9.
See no output on J6 with Oscilloscope guess one needs a Spectrum analyzer to view output waveform (Yes or No).

0 Walter Washington over 7 years ago in reply to Walter Washington

Prodigy 80 points

Followed all steps and now have spectrum analyzer connected see nothing

0 Walter Washington over 7 years ago in reply to Walter Washington

Prodigy 80 points

I am using CMODE3 and with DAC38RF8xEVM GUI set to DAC38RF82.
Followed all steps in section 2.1.4, 2.1.5 and 2.1.6

still receiving error:

Current lane rate is 3.84G
JESD reference clock from device EVM
to TSW14J56RevD needs to be set at 96M

Would like to discuss over telephone. Please call 949.300.9800. It would be greatly appreciated

0 Walter Washington over 7 years ago in reply to Walter Washington

Prodigy 80 points

Sent email to Ebenezer as requested on 20 Sept 2017.
Any and all feedback would be greatly appreciated.

0 Steve-Wilson over 7 years ago in reply to Walter Washington

TI__Mastermind 30200 points

Hi Walter, has someone gotten back to you by phone? let me know either way as I want to make sure that you get the support you need.

best regards,
-Steve Wilson

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TSW14J56EVM: HSDC Pro SW Freezes when run using TSW14J56RevD & DAC38RF8xEVM (windows-7) operating System